Low Resource FPGA Based Time-to-Digital Converter

For the precise measurement of the time difference between the arrival of different signals coming from the different channels, the time-to-digital converter (TDC) implemented in Field Programmable Gate Array (FPGA) is a very useful device. The TDC implemented so far are  basically tapped delay lines which provides a resolution of about 10 ps however such high resolution is necessary for some specific applications. So a low resource TDC implemented in FPGA is preferred which helps to measure the time difference between the signals.Keywords: analog-to-digital converter (ADC), resolution, DPLL, clock generation, jitte

Counter-Based and MUX-Based Design of DPLL, a Comparative Study

The design of modern day communication system emphasizes on transmission and proper reception of data at minimum possible error rates and also at the same time on maintenance of high degrees of precision. But there are additional factors that add to it such as the operating speeds of the communication device developed should be compatible with the other sub-systems of the setup. Also, the design complexity of the device and the cost of design should be minimum. So, based on the various factors as mentioned above, a situation arises where a number of designs can be put forward for the same device having their sets of merits and demerits. As such, an analysis of these different designs is essential to derive an optimal solution which is the main objective of this work. Considering the various constraints at hand, we would like to put forward a comparative study between two different designs of the communication receiver device DPLL, namely the counter based DPLL and Multiplexer based DPLL design which brings to light the merits of one design over the other in terms of key parameters such asspeed, design, complexity, hardware requirement etc.Keywords: Multiplexer, oscillator, detector, phase, recover