Statistical Anomalies of Bitflips in SRAMs to Discriminate SBUs From MCUs

International audienceRecently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Field Programmable Gate Arrays (FPGAs) and the original authors indicate that it is also valid for SRAMs. This paper presents a modified methodology that is based on checking the XORed addresses with bitflips, rather than on the difference. Irradiation tests on CMOS 130 & 90 nm SRAMs with 14-MeV neutrons have been performed to validate this methodology. Results in high-altitude environments are also presented and cross-checked with theoretical predictions. In addition, this methodology has also been used to detect modifications in the organization of said memories. Theoretical predictions have been validated with actual data provided by the manufacturer

Neutron-induced single events in a cots soft-errir free SRAM at low bias voltage

IEEE Catalog Number: CFP15449-ART (XPLORE) ISBN: 978-1-5090-0232-0 (XPLORE) IEEE Catalog Number: CFP15449-CDR (CD-ROM) ISBN: 978-1-5090-0230-6 (CD-ROM) IEEE Catalog Number: CFP15449-PRT (PRINT) ISBN: 978-1-5090-0231-3 (PRINT)International audienceThis paper presents an experimental study of the sensitivity to 15-MeV neutrons at low bias voltage of advanced low-power SRAMs by Renesas Electronics. The most interesting results are the occurrence of clusters of bitflips, hard errors only visible at low voltage, appearing along with single event upsets. The physical mechanisms are briefly discussed

Some Properties of only-SBUs Scenarios in SRAMs Applied to the Detection of MCUs

International audienceStatistical properties of experiments in SRAMs with only SBUs are mathematically evaluated. Strategies using deviations of actual data from theory are proposed to extract MCUs from the bulk of errors regardless the SRAM internal structure