5 research outputs found

    Thermal Conduction across Metalā€“Dielectric Sidewall Interfaces

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    The heat flow at the interfaces of complex nanostructures is three-dimensional in part due to the nonplanarity of interfaces. One example common in nanosystems is the situation when a significant fraction of the interfacial area is composed of sidewalls that are perpendicular to the principal plane, for example, in metallization structures for complementary metal-oxide semiconductor transistors. It is often observed that such sidewall interfaces contain significantly higher levels of microstructural disorder, which impedes energy carrier transport and leads to effective increases in interfacial resistance. The impact of these sidewall interfaces needs to be explored in greater depth for practical device engineering, and a related problem is that appropriate characterization techniques are not available. Here, we develop a novel electrothermal method and an intricate microfabricated structure to extract the thermal resistance of a sidewall interface between aluminum and silicon dioxide using suspended nanograting structures. The thermal resistance of the sidewall interface is measured to be āˆ¼16 Ā± 5 m<sup>2</sup> K GW<sup>ā€“1</sup>, which is twice as large as the equivalent horizontal planar interface comprising the same materials in the experimental sample. The rough sidewall interfaces are observed using transmission electron micrographs, which may be more extensive than at interfaces in the substrate plan in the same nanostructure. A model based on a two-dimensional sinusoidal surface estimates the impact of the roughness on thermal resistance to be āˆ¼2 m<sup>2</sup> K GW<sup>ā€“1</sup>. The large disparity between the model predictions and the experiments is attributed to the incomplete contact at the Alā€“SiO<sub>2</sub> sidewall interfaces, inferred by observation of underetching of the silicon substrate below the sidewall opening. This study suggests that sidewall interfaces must be considered separately from planar interfaces in thermal analysis for nanostructured systems

    Energy-Efficient Phase-Change Memory with Graphene as a Thermal Barrier

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    Phase-change memory (PCM) is an important class of data storage, yet lowering the programming current of individual devices is known to be a significant challenge. Here we improve the energy-efficiency of PCM by placing a graphene layer at the interface between the phase-change material, Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> (GST), and the bottom electrode (W) heater. Graphene-PCM (G-PCM) devices have āˆ¼40% lower RESET current compared to control devices without the graphene. This is attributed to the graphene as an added interfacial thermal resistance which helps confine the generated heat inside the active PCM volume. The G-PCM achieves programming up to 10<sup>5</sup> cycles, and the graphene could further enhance the PCM endurance by limiting atomic migration or material segregation at the bottom electrode interface

    Direct Visualization of Thermal Conductivity Suppression Due to Enhanced Phonon Scattering Near Individual Grain Boundaries

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    Understanding the impact of lattice imperfections on nanoscale thermal transport is crucial for diverse applications ranging from thermal management to energy conversion. Grain boundaries (GBs) are ubiquitous defects in polycrystalline materials, which scatter phonons and reduce thermal conductivity (Īŗ). Historically, their impact on heat conduction has been studied indirectly through spatially averaged measurements, that provide little information about phonon transport near a single GB. Here, using spatially resolved time-domain thermoreflectance (TDTR) measurements in combination with electron backscatter diffraction (EBSD), we make localized measurements of Īŗ within few Ī¼m of individual GBs in boron-doped polycrystalline diamond. We observe strongly suppressed thermal transport near GBs, a reduction in Īŗ from āˆ¼1000 W m<sup>ā€“1</sup> K<sup>ā€“1</sup> at the center of large grains to āˆ¼400 W m<sup>ā€“1</sup> K<sup>ā€“1</sup> in the immediate vicinity of GBs. Furthermore, we show that this reduction in Īŗ is measured up to āˆ¼10 Ī¼m away from a GB. A theoretical model is proposed that captures the local reduction in phonon mean-free-paths due to strongly diffuse phonon scattering at the disordered grain boundaries. Our results provide a new framework for understanding phononā€“defect interactions in nanomaterials, with implications for the use of high-Īŗ polycrystalline materials as heat sinks in electronics thermal management

    Temperature-Dependent Thermal Boundary Conductance of Monolayer MoS<sub>2</sub> by Raman Thermometry

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    The electrical and thermal behavior of nanoscale devices based on two-dimensional (2D) materials is often limited by their contacts and interfaces. Here we report the temperature-dependent thermal boundary conductance (TBC) of monolayer MoS<sub>2</sub> with AlN and SiO<sub>2</sub>, using Raman thermometry with laser-induced heating. The temperature-dependent optical absorption of the 2D material is crucial in such experiments, which we characterize here for the first time above room temperature. We obtain TBC āˆ¼ 15 MW m<sup>ā€“2</sup> K<sup>ā€“1</sup> near room temperature, increasing as āˆ¼ <i>T</i><sup>0.65</sup> in the range 300āˆ’600 K. The similar TBC of MoS<sub>2</sub> with the two substrates indicates that MoS<sub>2</sub> is the ā€œsofterā€ material with weaker phonon irradiance, and the relatively low TBC signifies that such interfaces present a key bottleneck in energy dissipation from 2D devices. Our approach is needed to correctly perform Raman thermometry of 2D materials, and our findings are key for understanding energy coupling at the nanoscale
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