Exploiting Existing Copies in Register File for Soft Error Correction

Soft errors are an increasingly important problem in contemporary digital systems. Being the major data holding component in contemporary microprocessors, the register file has been an important part of the processor on which researchers offered many different schemes to protect against soft errors. In this paper we build on the previously proposed schemes and start with the observation that many register values already have a replica inside the storage space. We use this already available redundancy inside the register file in combination with a previously proposed value replication scheme for soft error detection and correction. We show that, by employing schemes that make use of the already available copies of the values inside the register file, it is possible to detect and correct 39.0 percent of the errors with an additional power consumption of 18.9 percent

Avoiding register file inefficiency in terms of power and reliability

İşlemcinin yazmaç öbeği birçok bileşenle çeşitli aşamalarda etkileşim içinde olduğundan, işlemci veri-yolunun en aktif yapılarından birisidir. Buna rağmen yazmaç öbeği enerji ve veri yedekliliği bağlamında yeterince optimize edilmemiştir. Çalışmalarımızda hedefimiz ilk kısımda yazmaç öbeğinin enerji verimsizliğini optimize etmek ve ikinci kısımda gereksiz yazmaç yedekliliğinden daha yüksek güvenilirlik için istifade etmektir. Çağdaş mimarilerde yazmaç öbeği işlemcinin en çok enerji harcayan ve en çok kullanılan bileşenlerinden biridir. Bu nedenle yazmaç öbeğinin güç tüketimini azaltmak son derece önemlidir. Bu tezde, değişmeyen bitlere yazmayarak yazmaç öbeğinin enerji sarfiyatını azaltan tasarımlar öneriyoruz. Tasarımlarımız, yazmaç bitlerinin her işlemde ortalama sadece % 10'unun değiştiği gözlemine dayanmaktadır. Çalışmamızda, yazmaç öbeğinin yazma gücünü güncelleme-tabanlı bir yapıyla azaltmak için bu verimsizliği asgariye indiren mimari ve devresel teknikler önermekteyiz. 64-bitlik bir veri-yolunda, yazmaç öbeğinin enerji kaybının bazı gösterge programlar için % 24,85'e kadar ve tümünün ortalamasında % 20,59 seviyesinde azaltılabilmesinin ihmal edilebilir bir başarım kaybıyla mümkün olduğunu göstermekteyiz. Kozmik parçacıklar veya tümdevrenin paketleme malzemesinden kaynaklı radyasyon nedeniyle oluşan geçici hatalar, giderek önemi artan bir tasarım problemidir. Küçülen transistör kapı uzunluklarıyla birlikte sırasız çok-yollu boru-hattındaki veri-yolu bileşenleri geçici hatalara karşı daha da yatkın hale gelmektedir. Çağdaş mikro-işlemcilerdeki veri saklayan başlıca yapı olan yazmaç öbeği, araştırmacıların geçici hatalara karşı korumak için çok sayıda tasarım önerdikleri önemli işlemci kısımlarından olmuştur. Çalışmamıza yazmaç öbeğindeki kayıtlı değerlerin birçoğunun birbiriyle arasındaki Hamming uzaklıklarının çok az olduğu gözlemiyle başladık. Bu analiz sonuçlarını gösterdikten sonra sıfır Hamming uzaklığındaki yazmaç değerlerinin varlığından istifade eden bir geçici hata düzeltme yöntemi önerisi ortaya koyduk. Zaten mevcut olan bu yedekliliği parite korumasıyla birlikte kullanarak kaydedilmiş bir çok değeri düzeltme imkanını yakalamaktayız. Yöntemimizin kapsamasını genişletmek için aynı zamanda aralarındaki Hamming uzaklığı az olan değerler için de koruma sağlamayı öneriyoruz. Sonuçlarımız, yazmaç öbeğinde zaten mevcut olan kopyalardan istifade eden mekanizmaları kullanarak yazmaçların % 20,5'inin güç tüketiminde yalnızca % 2,8 artışla geçici hatalardan korunabildiğini göstermektedir. Bu yönteme aktif yazmaçları boşta olan yazmaçlara kopyalayan bir ilave mekanizmayı da eklersek, % 18,9 artan bir güç tüketimiyle yazmaç öbeğinin koruma kapsamı % 44,1'e yükselir. Kopyalama yerine en alt baytında sadece birkaç biti birbirinden farklı olan değerlerden istifade ederek kapsamayı önemsiz bir güç artışıyla % 39,8'e çıkarmak da mümkündür.Processor register file is one of the most active structures of the processor datapath, interacting with many components in several pipeline stages. However register file has not been well-optimized in terms of energy and data redundancy. In our studies, our goal is to optimize its energy inefficency in the first part and to exploit the inefficient register redundancy for better reliability in the second part. In modern architectures the register file is one of the most energy consuming and frequently used components of the processor. Therefore, reducing the register file power dissipation is critical. In this thesis, we propose schemes that reduce the energy dissipation of the register file by not writing the bits that are not changed. Our schemes rely on the observation that on the average only 10% of the register bits are changed by the instructions at each operation. In this study, we propose a combination of architectural and circuit level techniques that exploit this inefficiency for the register file's write power reduction using an update-based scheme. We show that for a 64-bit datapath it is possible to reduce the energy dissipation of the register file up to 24.85% for individual benchmark programs and by 20.59% on the average across all simulated benchmarks with a negligible performance compromise. Soft errors caused by the cosmic particles or the radiation from the packaging material of the integrated circuits are an increasingly important design problem. With the shrinking feature sizes, the datapath components of the out-of-order superscalar pipeline are becoming more prone to soft errors. Being the major data holding component in contemporary microprocessors, the register file has been an important part of the processor on which researchers offered many different schemes to protect against soft errors. We start with the observation that many of the stored values inside the register file have very small Hamming distances when compared to each other. After showing this analysis results we propose a soft error correction scheme that makes use of the presence of multiple register values that have zero Hamming distance from each other. We use this already available redundancy along with parity protection to achieve error correction for many of the stored values. We also extend the coverage of our scheme to offer coverage for values that are small hamming distances apart from each other. Our results show that, by employing schemes that make use of the already available copies of the values inside the register file, it is possible to protect 20.5% of the registers from soft errors with an additional power consumption of 2.8%. If we include the extension which duplicates active registers to idle registers to increase redundancy, protection coverage increases to 44.1% of the register file, with an increased power dissipation of 18.9%. Instead of duplicating, with negligible power overhead, it is possible to extend the coverage to 39.8% by exploiting the values that differ only a few bits in their least significant byte

Error Recovery Through Partial Value Similarity

29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2016 : Univ Connecticut, Storrs, CT)Soft errors arose as a critical problem for microprocessor designers due to shrinking feature sizes and increasing clock rates. Many attempts appeared to protect the register file which is the main storage component in modern microprocessors. Exploiting existing replica values in the register file is a recently proposed method to correct errors that occur on the register values. In this paper, with the observation that partial matches are clustered in the least significant bytes of the similar values in the register file, we propose to extend the coverage of existing replica based error correction schemes. Our schemes almost double the coverage of previously proposed mechanisms. The proposed method can recover 39.8% of the stored values in the register file by using this similarity and single-bit parity protection. The power overhead of this method constitutes only 3.1% of the register file's power budget

URFA-Update based register file architecture with partial register write for energy efficiency

In modern architectures the register file is one of the most energy consuming and frequently used components of the processor. Therefore, reducing the register file power dissipation is critical. In this paper, we propose schemes that reduce the energy dissipation of the register file by not writing the bits that are not changed. Our schemes rely on the observation that on the average only 10% of the register bits are changed by the instructions. In this study, we propose a combination of architectural and circuit level techniques that exploit this inefficiency for the register file's write power reduction using an update based scheme. We show that for a 64-bit datapath it is possible to reduce the energy dissipation of the register file up to 25% for individual benchmark programs and by 21% on the average across all simulated benchmarks with a negligible performance compromise. (C) 2016 Elsevier B.V. All rights reserved

Characterization of Context Switch Effects on L2 Cache

Multitasking is common in most systems. In order to use the processor resources efficiently, a multitasking system schedules processes to run for certain intervals by switching (saving and restoring) their contexts. However, since processes bring their own data to the cache when they are running, context switching causes each process to suffer from more cache misses. The behavior of L2 cache misses due to context switches activities under different cache configurations, working-set sizes, and process priorities has not been sufficiently investigated. Analysis of this behavior will give insights about the reasons and ways to mitigate these misses. The first contribution of this paper is the characterization of how context switch misses at the L2 cache is affected by process priorities. The paper also characterizes the context switch effect with various cache configurations, including the size and associativity of the cache. Finally, it defines two types of misses that occur due to context switches. Replacement context switch misses occur when a process ’ working set is replaced by an interfering process. Reorder context switch misses occur due to reordering of lines by an interfering process, i.e. moving lines from more recently used to less recently used position. Through the characterization, we found that the number of context switch misses signifi-cantly increases with lower priorities. On average, on a Linux operating system, a process with the lowest priority suffers 15.4 × more L2 cache misses due to the context switch ef-fect compared to when time-sharing is not used, while the process with a relatively higher priority suffers only 1.2 × more misses. In addition, we observed that the impact of con-text switch is affected more by the priority of the process itself, rather than the priority of the interfering process. We also observed that reorder context switch misses increase with higher associativity. Finally, the context switch effect is strongest when a process ’ working set size is close to the cache size