Courses timetabling based on hill climbing algorithm

In addition to its monotonous nature and excessive time requirements, the manual school timetable scheduling often leads to more than one class being assigned to the same instructor, or more than one instructor being assigned to the same classroom during the same slot time, or even leads to exercise in intentional partialities in favor of a particular group of instructors. In this paper, an automated school timetable scheduling is presented to help overcome the traditional conflicts inherent in the manual scheduling approach. In this approach, hill climbing algorithms have been modified to transact hard and soft constraints. Soft constraints are not easy to be satisfied typically, but hard constraints are obligated. The implementation of this technique has been successfully experimented in different schools with various kinds of side constraints. Results show that the initial solution can be improved by 72% towards the optimal solution within the first 5 seconds and by 50% from the second iteration while the optimal solution will be achieved after 15 iterations ensuring that more than 50% of scientific courses will take place in the early slots time while more than 50% of non-scientific courses will take place during the later time's slots

Accurate leakage current models for MOSFET nanoscale devices

This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB).In addition, the leakage resources due to the aggressive reduction in the oxide thickness

The Influence of the Nanometer Technology on Performance of CPL Full Adders

Abstract — In this paper the performance of 8-transistor based Full adder is analyzed, evaluated, and compared with that of three different types of Full Adders based on Complementary Pass Transistor XOR Logic gate. Simulation results using nano-scale SPICE parameters are obtained for the above mentioned FAs. It is shown that the performance of the 8-transistor based Full adder in term of power dissipation is superior to that of the other FAs. Multi-Supply Voltage Technique is used to optimize the outputs of 8-Transistor Full Adder. A new technique based on minimum leakage vector is proposed to reduce the leakage current when the circuit is in its off state

High-throughput implementation of the RIPEMD-160

One-way hash functions are the main cryptographic primitives which are used in the network protocols for user authentication and message integration. In the literature, implementations have been proposed either in hardware or software. The rich number of implementations is expected considering the number of constraints of a target application. When the target is to service more and more users-clients and thus the increase of their throughput, a hardware implementation is dictated. In this paper, RIPEMD-160 hash function is considered and a technique to increase its throughput. This technique involves the application of algorithmic transformations in space and time. The proposed technique leads to an increased throughput by 35% when compared to conventional implementations. Copyright © 2009 Inderscience Enterprises Ltd