Fast prediction of voltage stability index based on radial basis function neural network: Iraqi super grid network, 400-kV

With the increase in power demand and limited power sources has caused the system to operate at its maximum capacity. Therefore, the ability of determine voltage stability before voltage collapse has received a great attention due to the complexity of power system. In this paper a prediction of voltage stability index (VSI) based on radial basis function neural network (RBFNN) for the Iraqi Super Grid network, 400KV. Learning data has been obtained for various settings of load variables using load flow and conventional FVSI method. The input data was performed by using a 135 samples test with different bus voltage (Vb), Bus active and reactive power (Pb, Qb), bus load angle (?b) and FVSIij. The RBFNN model has four input representing the (Vb, Pb, Qb and ?b), sixteen nodes at hidden layer and one output node representing FVSIij have been used to assess the security on line. The proposed method has been tested in the IEEE 30 and a practical system. In Simulation results show that the proposed method is more suitable for on-line voltage stability assessment in term of automatically detection of critical transmission line when additional real or reactive loads are added

Optimal placement of DSTATCOM in distribution network based on load flow and voltage stability indices studies

The power utilities are experiencing a new challenge as the demand for electrical power is increasing on a regular basis. This forced the existing networks operates closed to its stability limits. The ability of a power system to remain acceptable magnitude voltages at all bus under both normal and contingency conditions, known as voltage stability is the major concern for both transmission and distribution network to ensure that a secure and reliable electrical power is able to transmit from generation to load side. This can be mitigated by integrating Custom Power (CP) device on the existing transmission system. However, the location of CP device is significantly important to ensure adequate investment of CP device in networks that will enhance the voltage stability margin, reduce power loss and improve voltage profile. In this paper, the optimal location of Distribution Static Synchronous Compensator (DSTATCOM) is introduced by analyzing results obtained from two studies; load flow and voltage stability indices. The studies were examined using the modified IEEE 30 bus system which is modelled and tested using DigSILENT PowerFactory 16 as simulation tools

Reconfigurable Enhanced Path Metric Updater Unit for Space Time Trellis Code Viterbi Decoder

Space Time Trellis Code (STTC) encoding and decoding techniques are effective for delivery of a reliable information because of the signal to noise ratio is very small. Even though the Viterbi algorithm is complicated to be designed, these methods typically used large memory space to store the information that have been processed mainly at the Path Metric Updater (PMU). Therefore, an effective memory management technique is one of the key factors in designing the STTC Viterbi decoder for low power consumption applications. This paper proposed the PMU memory reduction technique especially on Traceback activities that usually required a lot of memories for storing the data that has been processed in the past part by using Altera Quartus 2 and 0.18 µm Altera CPLD 5M570ZF256C5 as targeted hardware. Through this method, the reduction achieved at least 66% of memory requirements and 75% improvements in processing time without a significanct effects on the outputs results of the STTC Viterbi Decoder for 4-PSK modulation technique by using 50MHz clocks

Adaptive notch filter under indirect and direct current controls for active power filter

This study presents the implementation of adaptive notch filter (ANF) as reference signal extraction for shunt active power filter (APF) in indirect current control (ICC) and direct current control (DCC) modes for three phase system. The ANF functions to filter the signal that inputted to it by producing a fundamental signal and harmonics signal. The advantage of applying the ANF algorithm is based on its simple design that giving the ANF advantages to be utilize in microcontroller. The performance of the ANF is validated though MATLAB simulation in ICC dan DCC configurations. Based on the simulation results, the ANF is capable to work efficiently for both ICC and DCC modes, but in term of efficiency, the ICC mode is clearly showing a better harmonics mitigation result. Base on the result also it shown that the ANF is capable of mitigate the harmonics below the standard required by the IEEE 519-92. The application of ANF is useful to be applied due to its simple design and filtering method

Reconfigurable enhanced path metric updater unit for Space Time Trellis Code Viterbi decoder

Space Time Trellis Code (STTC) encoding and decoding techniques are effective for delivery of a reliable information because of the signal to noise ratio is very small. Even though the Viterbi algorithm is complicated to be designed, these methods typically used large memory space to store the information that have been processed mainly at the Path Metric Updater (PMU). Therefore, an effective memory management technique is one of the key factors in designing the STTC Viterbi decoder for low power consumption applications. This paper proposed the PMU memory reduction technique especially on Traceback activities that usually required a lot of memories for storing the data that has been processed in the past part by using Altera Quartus 2 and 0.18 µm Altera CPLD 5M570ZF256C5 as targeted hardware. Through this method, the reduction achieved at least 66% of memory requirements and 75% improvements in processing time without a significant effects on the outputs results of the STTC Viterbi Decoder for 4-PSK modulation technique by using 50MHz clocks