A self-aligned gate definition process with submicron gaps

A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected

Metal contacts to lowly doped Si and ultra thin SOI

We present our investigations on the fabrication of ohmic and Schottky contacts of several metals on lowly doped bulk Si and SOI wafers. Through this paper we evaluate the fabrication of rectifying devices in which no doping is intentionally introduced

Barrier properties of ALD W_1.55N thin films

W1.5N films grown by ALD from WF6, NH3, C2H4 and SiH4 as precursors were tested as Cu diffusion barriers in p+/n diodes and capacitors with SiO2 as a dielectric. I-V and C-V, C-t characteristics were measured before and after anneal. The layers exhibit excellent barrier properties against both Cu and Al interaction with silicon. No changes of current and capacitance attributed to a barrier failure were observed after annealing at 400°C. Samples without the barrier showed a drastic change of the I-V characteristics. The composition of the films was W1.5N as determined with RBS, being a mixture of WN and W2N phases The RMS- roughness was as low as 0.5-0.7 nm for a film with a thickness of 25 nm.</p

Low-temperature process steps for realization of non-volatile memory devices

In this work, the low-temperature process steps required for the realization of nano-crystal non-volatile memory cells are discussed. An amorphous silicon film, crystallized using a diode pumped solid state green laser irradiating at 532 nm, is proposed as an active layer. The deposition of the subsequent functional layers (e.g., gate oxide) can be done using CVD and ALD reactors in a cluster tool. We show that a high nanocrystal density (Si-NC), required for a good functionality of the memory device, can be obtained by using disilane (Si2H6) or trisilane (Si3H8, known as Silcore®) as precursors for LPCVD instead of silane, at a deposition temperature of 325 °C. The nanocrystals are encapsulated with an ALD-Al2O3 layer (deposited at 300 °C), which serves as oxidation barrier. The passivation of the realized structure is done with an ALD-TiN layer deposited at 425 °C. In this work, we realized Al/TiN/Al2O3/Si-NC/SiO2/Si(100) multilayer floating-gate structures, where the crystallized amorphous silicon film was for the time being replaced by a mono-crystalline silicon wafer, and the gate oxide was thermally grown instead of a low-temperature PECVD oxide. The structures were characterized in terms of their performance as memory cells. In addition, the feasibility to use laser crystallization for improving the amorphous silicon films (prior to the gate oxide deposition) was explored

Complementary vertical bipolar transistor process using high-energy ion implantation

High-energy ion implantation is used as a key processing step in the formation of a complementary bipolar process with both transistor types being vertical. Both n-p-n and p -n-p transistors are made vertically with a deep implanted collector region. Combinations of epitaxial and buried layers are avoided. Both transistors have an ideal Gummel plot with a current gain of about 60. Cutoff frequencies of over 1 GHz have been measured, which is much higher than for conventional lateral p-n-p transistor

Atomic layer deposition of W - based layers on SiO2

W<Si> and W1-xNx , where x= 15- 22 at%, thin films were grown using the ALD (Atomic Layer Deposition) principle. Growth rate of W<Si> films is about 4- 5 monolayers/ cycle at 300- 350 ºC. Growth rate of W1-xNx is 0.5 monolayer/cycle at 325- 350 ºC. Standard Deviation (STDV) of thickness is about 2% for 20nm layers. Specific resistivity is 180 mW cm for W<Si> and as low as 220-340 mWcm for W1-xNx 20nm films. 4- point probe sheet resistivity test is applied to Cu/ Barrier/ SiO2 stacks with ramping temperature. No changes of normalized resistance reflecting Cu-Barrier interaction was measured after 500 ºC annealing cycl