Improving the power-delay performance in subthreshold source-coupled logic circuits

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18$\mu$m CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated

Mems inertial power generators for biomedical applications

Accepted versio

Lake Lanier-Clean Lakes Project : discrete pollutant sources

Issued as Draft final report, and Final report, Project no. E-20-M0

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Subthreshold design has been proposed as an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. In this paper we propose a subthreshold FIR architecture which brings the benefits of reducedleakage energy, reduced minimum energy point, reduced operating voltage and increased operating frequency when compared with recently reported subthreshold designs. We shall demonstrate this through the design of a 9-tap FIR filter operating at 220mV with operational frequency of 126kHz/sample consuming 168.3nW or 1.33pJoules/sample. Furthermore, the area overhead of the proposed method is less than that of the transverse structure often employed in subthreshold filter designs. For example, a 9-tap filter based on transverse structure has 5X higher area than the filter designed using our proposed method

Filtration and backwashing of biological filters

Issued as Report, Project no. E-20-G28Report has author: Rashad AhmadReport has title: Filtration and backwashing of biological filter