Yield-improving test and routing circuits for a novel 3-D interconnect technology

This work presents a system to increase the yield of a novel 3-D chip integration technology. A built-in self-test and a routing system have been developed to identify and avoid faults on vertical connections between different stacked chips. The 3-D technology is based on stacking several active CMOS-ICs, which have through-substrate electrical contacts to communicate with each other. The expected defects of these vias are shorts and resistances that are too high. <P> The test and routing system is designed to analyze an arbitrary number of connections. The result ist used to gain information about the reliability of the new 3-D processing and to increase its yield. The circuits have been developed in 0.13 μm technology, one chip has been fabricated and tested, another one is in production

Eine Test- und Ansteuerschaltung für eine neuartige 3D Verbindungstechnologie

In der vorliegenden Arbeit wird eine Built-In Self-Test Schaltung (BIST) vorgestellt, welche die vertikalen Inter-Chip-Verbindungen in einer neuartigen 3D Schaltungstechnologie auf ihre Funktionalität zur Datenübertragung überprüft. Die 3D Technologie beruht auf der Stapelung mehrerer aktiver Silizium-CMOS-ICs, welche durch das Siliziumsubstrat hindurch vertikal miteinander elektrisch verbunden sind. Bei diesen Vias sind die zu erwartenden Defekte hochohmige Verbindungen und Kurzschlüsse. </p><p style=&quot;line-height: 20px;&quot;> Die entwickelte Testschaltung ermöglicht es, beliebige Konstellationen von vertikalen Verbindungen auf Fehler zu untersuchen, und das Ergebnis entweder zur Analyse der 3D Technologie auszulesen oder innerhalb des Chipstapels zu verwenden, um defekte Vias zu umgehen. Die Schaltung wurde in einer 0,13μm Technologie entworfen und simuliert. Ein Testchip ist momentan in Produktion

Mixed mode VLSI implementation of a neural associative memory

Heittmann A, Rückert U. Mixed mode VLSI implementation of a neural associative memory. In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on. IEEE Comput. Soc; 1999: 299-306.A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a n×m matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. Although analog circuits suffer from device mismatch a moderate precision of the circuit is acceptable since for the given associative memory model only few parts of the circuit participate on the performed information processing steps. Thus, the information processing elements can be integrated very densely on one chip and hence large scale integration with a large number of connection weights is feasibl

Implementing Neural Soft- And Hardware On The Autonomous Mini-robot Khepera

Loffler A, Klahold J, Heittmann A, Witkowski U, Rückert U. Implementing Neural Soft- And Hardware On The Autonomous Mini-robot Khepera. In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on. IEEE Comput. Soc; 1999: 425-426.The applicability of neural networks to generate complex behaviour on autonomous systems is demonstrated both at soft- and hardware-level. In particular, the emergence of simple behaviors based on the Braitenberg approach, adaptive sensor calibration by self-organizing maps with a comparison between off- and online learning and a visualisation tool for a posteriori analysis are shown. It is also envisaged to present the working of embedded neural hardware as associative memory and self-organizing maps. In this connection, the mini-robot Khepera serves as an exemplary platfor

Digital VLSI Implementation of a Neural Associative Memory

Heittmann A, Malin J, Pintaske C, Rückert U. Digital VLSI Implementation of a Neural Associative Memory. In: Klar H, König A, Ramacher U, eds. Proceedings of the 6th International Conference on Microelectronics for Neural Network, Evolutionary and Fuzzy Systems. Dresden, Germany; 1997: 280-285

Stateful Three-Input Logic with Memristive Switches

Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation