Performance analysis of ultrathin junctionless double gate vertical MOSFETs

The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability

Design 4-to-1 multiplexer using universal gate with standard process technology

Nowadays, CMOS is widely being used in integrated circuit design. In this project, the original 4-to-1 multiplexer schematic is redesign by changing the gate inside the multiplexer with CMOS universal gate. NAND gate will be used as the universal gate in this project. Through this project, SILVACO EDA tools are used to design the integrated circuit, schematic and layout. The schematic of NAND gate and 4-to-1 multiplexer is analyzed in order to meet the specification based on datasheet of NAND gate and 4-to-1 multiplexer. The result of the analyses can be used to determine the size of the transistors. The size of transistors can be used to design the layout of NAND and 4-to-1 multiplexer. At the end of the project, a new design of 4-to-1 multiplexer using universal gate will be produced and it meets the specification required in the datasheet of 4-to-1 multiplexer. Moreover, the equivalent layout of 4-to-1 multiplexer will also be produced