Switched-current filter structure for synthesizing arbitrary characteristics based on follow-the-leader feedback configuration

This document is the Accepted Manuscript version of the following article: Wenshan Zhao, Yigang He, and Yichuang Sun, ‘Switched-current filter structure for synthesizing arbitrary characteristics based on follow-the-leader feedback configuration’, Analog Integrated Circuits and Signal Processing, (2015), Vol. 82 (2): 479-486. The version of record is available online at doi: 10.1007/s10470-014-0477-8 © Springer Science+Business Media New York 2015Peer reviewedFinal Accepted Versio

Analogue micropower FET techniques review

Accepted versio

Slew rate induced distortion in switched-resistor integrators

Opamp-RC integrators built with linear resistors and capacitors can achieve very high linearity. By means of a switched resistor, tuning of the RC time-constant is possible via the duty-cycle of the clock controlling the switched resistor. This paper analyzes the effect of opamp slew rate limitations on the distortion of a switched-resistor lossy opamp-RC integrator. We show via analysis and simulations that the use of two sets of switched resistors instead of one relaxes the opamp slew rate requirements, and reduces the resulting distortion significantly

Theoretical analysis of highly linear tunable filters using Switched-Resistor techniques

In this paper, an in-depth analysis of switched-resistor (S-R) techniques for implementing low-voltage low-distortion tunable active-RC filters is presented. The S-R techniques make use of switch(es) with duty-cycle-controlled clock(s) to achieve tunability of the effective resistance and, hence, the RC time constant. The characteristics of two S-R networks utilizing one set (S-1R) and two sets (S-2R) of switch and resistor combinations are analyzed. It will be shown that the S-2R network outperforms the S-1R counterpart in terms of finite-slew-rate-induced distortion, frequency translation, and noise performance. In order to extend the tuning range, an S-R bank scheme is also described. The theoretical analysis was verified by an experiment on a 100-kHz first-order S-R filter prototype, implemented using discrete elements, where several advantages of the S-2R over the S-1R networks are demonstrated. Simulations of 10-MHz low-pass filters based on the S-1R\ud and S-2R techniques in a standard 0.18- mCMOSprocess are also included for performance comparison in practical on-chip filter implementations