34 research outputs found

    High Performance Channel Model Hardware Emulator for 802.11n"

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    In this paper, the design and implementation of a new high performance hardware channel emulator is presented. The purpose of the developed emulator is to efficiently reproduce in a laboratory environment the accurate behaviour of several effects of the radio channel over a multiple antennas wireless communication system, including AWGN (additive white Gaussian noise), multipath, attenuation and Doppler shift. The main application target is the test and the performance evaluation of a new 802.11n transceiver. The prototype has been implemented on a board including both an ARM processor and a field programmable gate array (FPGA), and it supports the simulation of a 40 MHz radio frequency bandwidth

    A reconfigurable, power-scalable Rake receiver IP for W-CDMA

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    During the last few years, the wireless market has experienced an exponential growth. 2G systems are essentially voice-oriented: the main innovation expected from 3G ones is the ubiquitous Internet and multimedia fruition. The transition from 2G to 3G provides both opportunities and challenges: one way to make this migration as smooth as possible relies on the employment of reconfigurable architectures. In this paper, a reconfigurable Rake receiver for W-CDMA is proposed. Very promising results from the physical implementation on a XCV300E have been obtained
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