On the Design of a Linear Delay Element for the Triggering Module at CERN LHC

This paper presents an analytical model of a linear delay element circuit to be employed in the triggering module for the High Momentum Particle Identification Detector (HMPID) at the CERN Large Hadron Collider (LHC). The aim of the analytical model is to facilitate the design of the linear delay element circuit, while maximizing its linearity and delay range. The analytical model avoids the need of time consuming parametric sweeps on the aspect ratios of the various transistors of the delay element in order to optimize it. In addition, the analytical model can be used to predict the variation of the delay with the input tuning voltage. The proposed analytical model is verified via the simulation of the delay element circuit using the 0.18 μm X-FAB technology

A Novel Very Low Voltage Topology to implement MCML XOR Gates

A new very low-voltage topology to implement MOS current mode logic (MCML) XOR gates is proposed in this paper. Instead of stacking several level of transistors to implement a two inputs XOR gate, a p-type differential pair is used to steer the current in n-type differential pairs through current mirrors. The proposed topology allows to reduce the minimum supply voltage of MCML XOR gates while guaranteeing a fully current mode behavior as in the conventional XOR gate. The proposed topology has been compared against the conventional and triple tail MCML XOR gates. Simulation results referring to a 40nm CMOS technology for VDD=1V confirm that the XOR gate presented in this work exhibits a lower propagation delay than the previously published low voltage MCML XOR gate. Furthermore both theoretical analysis and simulation results in a 40nm process show that the proposed topology is able to work with a VDD as low as 0.65V whereas state of the art topologies are not usable below 0.8V