High temperature RF behavior of SOI MOSFET transistors for Low Power Low Voltage applications

This paper presents a new approach to optimize the RF performance at high temperatures for low power low voltage applications. It is shown that the correct choice of the bias point can result in an improvement of the RF behavior of SOI transistors with increasing the temperature, which is opposite to the traditional degradation of RF behavior with increasing temperature. This approach is confirmed by RF measurements for both floating-body and body-tied SOI MOSFET transistors

Non-Linear analysis of n-type Schottky-Barrier MOSFETs

In the last few years, many efforts have been made looking for the improvement of the DC and RF performance of MOS transistors. In this scope, Schottky-Barrier transistors appear as very interesting alternative to conventional devices. In this paper we present the non-linear behavior of dopant segregated n-type SB-MOSFETs with 180 nm channel length

Comparison between the behavior of submicron Graded-Channel SOI nMOSFETs with Fully- and Partially-Depleted operations in a wide temperature range

In this work electrical properties of GC SOI nMOSEETs from two different technologies were presented for temperatures ranging between 90K and 380K. It has been shown that the increase of mobility with temperature reduction is larger than for devices with lighter dopind levels. Heavily doped GC from transistors shown constant threshold voltage over the entire temperature range, as it lies close to the ZTC point. Although the temperature lowering leads devices to operate in full depletion, GC devices with thin gate oxide presented GΓFBE effect due to the leakage current reduction. The subthreshold swing of heavily doped GC transistors have shown to depart the theoretical limit for T higher than 250K, indicating a change in the operation mode from fully to partially-depleted

Mobility improvement in nanowire junctionless transistors by uniaxial strain

Improvement of current drive in n- and p-type silicon junctionless metal-oxide-semiconductor-field-effect-transistors (MOSFETs) using strain is demonstrated. Junctionless transistors have heavily doped channels with doping concentrations in excess of 1019 cm−3 and feature bulk conduction, as opposed to surface channel conduction. The extracted piezoresistance coefficients are in good agreement with the piezoresistive theory and the published coefficients for bulk silicon even for 10 nm thick silicon nanowires as narrow as 20 nm. These experimental results demonstrate the possibility of enhancing mobility in heavily doped silicon junctionless MOSFETs using strain technology