Method And Apparatus Capable Of Compensating DC OffsetAnd Synchronization Using Preamble Signal

오프셋 검출 회로는 쉬프트 레지스터, 누산부 및 연산부를 포함한다. 쉬프트 레지스터는 입력 신호를 N 배 오버 샘플링 비율로 디지털 변환한 디지털 변환값을 순차적으로 입력받고 저장한다. 누산부는 디지털 변환값이 입력될 때마다 상기 디지털 변환값들 중 가장 최근의 N 개의 디지털 변환값들을 누산한 누산값을 갱신 및 저장한다. 연산부는 누산값을 기초로 상기 입력 신호의 논리 레벨이 천이되는지 판단하고, 상기 입력 신호의 논리 레벨이 천이하면 상기 누산값을 N으로 나눈 평균치를 직류 오프셋 레벨로 출력한다

시스템씨를 사용한 코시뮬레이션 방식의 시스템 성능 분석

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2002.2, [ iv, 60 p. ]The rapid improvement on silicon process technology allows a complex system to be integrated onto a single chip. This revolutionary System-on-Chip (SOC) paradigm enables unprecedented performance and functionality at a low cost, using the benefit of small size, low power consumption, etc. On the other hand, due to the increased scale and complexity of the target system, designing optimized architecture from the functional specification is becoming more and more difficult. Therefore simulation based performance analysis is the efficient method for the SOC design. In this paper I present a fast system performance analysis method based on co-simulation using SystemC. As concurrent operations between hardware and software increase, the I/O access latency caused by shared bus and memory contention affects entire system performance. I explained noble simulation framework that has timing information directly annotated from the commonly used high level functional specification method such as C/C++ with the help of SystemC. The simulation speed is only hundreds times slower than that of untimed functional execution, and the designer is offered good chances to examine how the architectural decision alters overall system performance rapidly. For designers to use our simulation framework conveniently, I addressed system component templates and tools for using these templates. Using the example of ADPCM and printer system, the efficiency and accuracy of our approach are tested, resulting in very similar behavior to the real system.한국과학기술원 : 전기및전자공학전공