6 research outputs found
Interpreted graph models
A model class called an Interpreted Graph Model (IGM) is defined. This class includes a large number of graph-based models that are used in asynchronous circuit design and other applications of concurrecy. The defining characteristic of this model class is an underlying static graph-like structure where behavioural semantics are attached using additional entities, such as tokens or node/arc states. The similarities in notation and expressive power allow a number of operations on these formalisms, such as visualisation, interactive simulation, serialisation, schematic entry and model conversion to be generalised. A software framework called Workcraft was developed to take advantage of these properties of IGMs. Workcraft provides an environment for rapid prototyping of graph-like models and related tools. It provides a large set of standardised functions that considerably facilitate the task of providing tool support for any IGM. The concept of Interpreted Graph Models is the result of research on methods of application of lower level models, such as Petri nets, as a back-end for simulation and verification of higher level models that are more easily manipulated. The goal is to achieve a high degree of automation of this process. In particular, a method for verification of speed-independence of asynchronous circuits is presented. Using this method, the circuit is specified as a gate netlist and its environment is specified as a Signal Transition Graph. The circuit is then automatically translated into a behaviourally equivalent Petri net model. This model is then composed with the specification of the environment. A number of important properties can be established on this compound model, such as the absence of deadlocks and hazards. If a trace is found that violates the required property, it is automatically interpreted in terms of switching of the gates in the original gate-level circuit specification and may be presented visually to the circuit designer. A similar technique is also used for the verification of a model called Static Data Flow Structure (SDFS). This high level model describes the behaviour of an asynchronous data path. SDFS is particularly interesting because it models complex behaviours such as preemption, early evaluation and speculation. Preemption is a technique which allows to destroy data objects in a computation pipeline if the result of computation is no longer needed, reducing the power consumption. Early evaluation allows a circuit to compute the output using a subset of its inputs and preempting the inputs which are not needed. In speculation, all conflicting branches of computation run concurrently without waiting for the selecting condition; once the selecting condition is computed the unneeded branches are preempted. The automated Petri net based verification technique is especially useful in this case because of the complex nature of these features. As a result of this work, a number of cases are presented where the concept of IGMs and the Workcraft tool were instrumental. These include the design of two different types of arbiter circuits, the design and debugging of the SDFS model, synthesis of asynchronous circuits from the Conditional Partial Order Graph model and the modification of the workflow of Balsa asynchronous circuit synthesis system.EThOS - Electronic Theses Online ServiceEPSRCGBUnited Kingdo
Power-compute co-design for robust pervasive IoT applications
PhD ThesisThe modern development of internet of things (IoT) requires the IoT devices to be more
compact and energy autonomous. Many of them require to be able to operate with
unstable and low power supplies that come from various energy sources such as energy
harvesters. This creates a challenge for building IoT devices that need to be robust to
energy variations.
In this research we propose methods for improving energy characteristics of IoT
devices from the perspective of two main challenges: (i) improving the efficiency
and stability of power regulators, and (ii) enhancing the energy robustness of the IoT
devices. The existing design methods do not consider these two aspects holistically. One
important feature of our approach is holistic use of event-based, temporal representation
of data, which involves using asynchronous techniques and duty-cycle-based encoding.
For power regulation we use switched-capacitor converters (SCC) because they offer
compactness and ease of on-chip implementation. In this research we adapt the existing
methods and develop new techniques for SCC design based on asynchronous circuits.
This allows us to improve their performance and stability. We also investigate the
methods of parasitic charge redistribution, and apply them to self-oscillating SCC,
improving their performance. The key contribution within (i) is development of the
methods of SCC design with improved characteristics.
The majority of novel IoT systems are shifting towards the “AI at the edge” vision,
for example, involving neural networks (NN). We consider a perceptron-based neural
network as a typical IoT computing device. In our research we propose a novel
NN design approach using the principle of pulse-width modulation (PWM). PWMencoded
signals represent information with their duty cycle values which may be made
independent of the voltages and frequencies of the carrier signals. As a result, the device
is more robust to voltage variations, and, thus, the power regulation can be simplified.
This is the second major contribution addressing challenge (ii).
The advantages of the proposed methods are validated with simulations in the
Cadence environment. The simulations demonstrate the operation of the designed
power regulators, and the improvements of their efficiency. The simulations also
demonstrate the principle of operation of the PWM-based perceptron and prove its
power and frequency elasticity.
The thesis gives future research directions into a deeper study of the holistic co-design
of a variation-robust power-compute paradigm and its impact on developing future IoT
applications
Multi-resource approach to asynchronous SoC : design and tool support
As silicon cost reduces, the demands for higher performance and lower power consumption are ever increasing. The ability to dynamically control the number of resources employed can help balance and optimise a system in terms of its throughput, power consumption, and resilience to errors. The management of multiple resources requires building more advanced resource allocation logic than traditional 1-of-N arbiters posing the need for the efficient design flow supporting both the design and verification of such systems. Networks-on-Chip provide a good application example of distributed arbitration, in which the processor cores needing to transmit data are the clients; and the point-to-point links are the resources managed by routers. Building fast and smart arbiters can greatly benefit such systems in providing efficient and reliable communication service. In this thesis, a multi-resource arbiter was developed based on the Signal Transition Graph (STG) development flow. The arbiter distributes multiple active interchangeable resources that initiate requests when they are ready to be used. It supports concurrent resource utilization, which benefits creating asynchronous Multiple-Input-Multiple- Output (MIMO) queues. In order to deal with designs of higher complexity, an arbiter-oriented design flow is proposed. The flow is based on digital circuit components that are represented internally as STGs. This allows designing circuits without directly working with STGs but allowing their use for synthesis and formal verification. The interfaces for modelling, simulation, and visual model representation of the flow were implemented based on the existing modelling framework. As a result, the verification phase of the flow has helped to find hazards in existing Priority arbiter implementations. Finally, based on the logic-gate flow, the structure of a low-latency general purpose arbiter was developed. This design supports a wide variety of arbitration problems including the multi-resource management, which can benefit building NoCs employing complex and adaptive routing techniques.EThOS - Electronic Theses Online ServiceEPSRC grant GR/E044662/1 (STEP)GBUnited Kingdo
Visualisation and analysis of complex behaviours using structured occurrence nets
PhD ThesisA complex evolving system consists of a large number of sub-systems
which may proceed concurrently and interact with each other or with
the external environment, while its behaviour is subject to modification
by other systems. Structured occurrence nets (sons) are a
Petri net based formalism for modelling the behaviour of complex
evolving systems. The concept extends that of occurrence nets, a
formalism that can be used to record causality and concurrency information
concerning a single execution of a system. In sons, multiple
occurrence nets are combined using various types of relationships in
order to represent dependencies between communicating and evolving
sub-systems.
The work presented in this thesis aims to develop a tool and extend existing
methodology for structured representations of the behaviours of
complex evolving system. The theoretical development focuses on the
extension of existing son concepts. It addresses the issue of efficient
son model checking and simulation, representations of alternative behaviour
and time information, structuring son-based unfolding, and
algorithms for constructing the unfolding. The implementation aims
to develop tools for son-based model visualisation, simulation and
analysis. An open source tool called SONCraft has been developed
to support these functionalities. SONCraft provides a user-friendly
graphical interface that facilitates model entry, supports interactive
visual simulation, and allows the use of a set of analytical tools for
model checking.supported in part by EPSRC EP/K001698/1 UNderstanding
COmplex system eVolution through structurEd behaviouRs
(UNCOVER) project
Compositional approach to design of digital circuits
PhD ThesisIn this work we explore compositional methods for design of digital circuits with
the aim of improving existing methodoligies for desigh reuse. We address compositionality
techniques looking from both structural and behavioural perspectives.
First we consider the existing method of handshake circuit optimisation via control
path resynthesis using Petri nets, an approach using structural composition. In
that approach labelled Petri net parallel composition plays an important role and
we introduce an improvement to the parallel composition algorithm, reducing the
number of redundant places in the resulting Petri net representations. The proposed
algorithm applies to labelled Petri nets in general and can be applied outside of the
handshake circuit optimisation use case.
Next we look at the conditional partial order graph (CPOG) formalism, an approach
that allows for a convenient representation of systems consisting of multiple
alternative system behaviours, a phenomenon we call behavioural composition. We
generalise the notion of CPOG and identify an algebraic structure on a more general
notion of parameterised graph. This allows us to do equivalence-preserving manipulation
of graphs in symbolic form, which simplifies specification and reasoning about
systems defined in this way, as displayed by two case studies.
As a third contribution we build upon the previous work of CPOG synthesis used
to generate binary encoding of microcontroller instruction sets and design the corresponding
instruction decoder logic. The proposed CPOG synthesis technique solves
the optimisation problem for the general case, reducing it to Boolean satisfiability
problem and uses existing SAT solving tools to obtain the result.This work was
supported by a studentship from Newcastle University EECE school, EPSRC grant
EP/G037809/1 (VERDAD) and EPSRC grant EP/K001698/1 (UNCOVER).
i