Pupil wavefront manipulation for the compensation of mask topography effects in optical nanolithography

As semiconductor optical lithography is pushed to smaller dimensions, resolution enhancement techniques have been required to maintain process yields. For some time, the customization of illumination coherence at the source plane has allowed for the control of diffraction order distribution across the projection lens pupil. Phase shifting at the mask plane has allowed for some phase control as well. However, geometries smaller than the imaging wavelength introduce complex wavefront effects that cannot be corrected at source or mask planes. Three dimensional mask topography effects can cause a pitch dependent defocus (δBF), which can decrease the useable depth of focus (UDOF) across geometry of varying density. Wavefront manipulation at the lens pupil plane becomes necessary to provide the degrees of freedom needed to correct for such effects. The focus of this research is the compensation of such wavefront phase error realized through manipulation of the lens pupil plane, specifically in the form of spherical aberration. The research does not attempt to improve the process window for one particular feature, but rather improve the UDOF in order to make layouts with multiple pitches possible for advanced technology nodes. The research approach adopted in this dissertation includes rigorous simulation, analytical modeling, and experimental measurements. Due to the computational expense of rigorous calculations, a smart genetic algorithm is employed to optimize multiple spherical aberration coefficients. An analytical expression is formulated to predict the best focus shifts due to spherical aberration applied in the lens pupil domain. Rigorously simulated trends of best focus (BF) through pitch and orientation have been replicated by the analytical expression. Experimental validation of compensation using primary and secondary spherical aberration is performed using a high resolution wavefront manipulator. Subwavelength image exposures are performed on four different mask types and three different mask geometries. UDOF limiting δBF is observed on the thin masks for contact holes, and on thick masks for both one directional (1D) and two directional (2D) geometries. For the contact holes, the applied wavefront correction decreases the δBF from 44 nm to 7 nm and increases the UDOF to 109 nm, an 18% improvement. For the 1D geometries on a thick mask, the through pitch UDOF is increased from 59 nm to 108 nm, an 83% improvement. Experimental data also shows that an asymmetric wavefront can be tuned to particular geometries, providing a UDOF improvement for line ends under restricted processing conditions. The experimental data demonstrates that pupil wavefront manipulation has the capability to compensate for mask topography induced δBF. This dissertation recommends that corrective spherical aberration coefficients be used to decrease pitch dependent best focus, increase process yield, and ultimately expand the design domain over parameters such as mask materials and mask feature densities. The effect of spherical aberration applied in the pupil plane is to provide a wavefront solution that is equivalent to complex multiple-level mask compensation methods. This will allow the advantages of thicker masks to be explored for further applications in semiconductor optical lithography

Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations

Electrical Design for Manufacturability Solutions: Fast Systematic Variation Analysis and Design Enhancement Techniques

The primary objectives in this research are to develop computer-aided design (CAD) tools for Design for Manufacturability (DFM) solutions that enable designers to conduct more rapid and more accurate systematic variation analysis, with different design enhancement techniques. Four main CAD tools are developed throughout my thesis. The first CAD tool facilitates a quantitative study of the impact of systematic variations for different circuits' electrical and geometrical behavior. This is accomplished by automatically performing an extensive analysis of different process variations (lithography and stress) and their dependency on the design context. Such a tool helps to explore and evaluate the systematic variation impact on any type of design. Secondly, solutions in the industry focus on the "design and then fix philosophy", or "fix during design philosophy", whereas the next CAD tool involves the "fix before design philosophy". Here, the standard cell library is characterized in different design contexts, different resolution enhancement techniques, and different process conditions, generating a fully DFM-aware standard cell library using a newly developed methodology that dramatically reduce the required number of silicon simulations. Several experiments are conducted on 65nm and 45nm designs, and demonstrate more robust and manufacturable designs that can be implemented by using the DFM-aware standard cell library. Thirdly, a novel electrical-aware hotspot detection solution is developed by using a device parameter-based matching technique since the state-of-the-art hotspot detection solutions are all geometrical based. This CAD tool proposes a new philosophy by detecting yield limiters, also known as hotspots, through the model parameters of the device, presented in the SPICE netlist. This novel hotspot detection methodology is tested and delivers extraordinary fast and accurate results. Finally, the existing DFM solutions, mainly address the digital designs. Process variations play an increasingly important role in the success of analog circuits. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. The fourth CAD solution, proposed in this thesis, introduces a variability-aware DFM solution that detects, analyze, and automatically correct hotspots for analog circuits

Design, Fabrication, and Run-time Strategies for Hardware-Assisted Security

Today, electronic computing devices are critically involved in our daily lives, basic infrastructure, and national defense systems. With the growing number of threats against them, hardware-based security features offer the best chance for building secure and trustworthy cyber systems. In this dissertation, we investigate ways of making hardware-based security into a reality with primary focus on two areas: Hardware Trojan Detection and Physically Unclonable Functions (PUFs). Hardware Trojans are malicious modifications made to original IC designs or layouts that can jeopardize the integrity of hardware and software platforms. Since most modern systems critically depend on ICs, detection of hardware Trojans has garnered significant interest in academia, industry, as well as governmental agencies. The majority of existing detection schemes focus on test-time because of the limited hardware resources available at run-time. In this dissertation, we explore innovative run-time solutions that utilize on-chip thermal sensor measurements and fundamental estimation/detection theory to expose changes in IC power/thermal profile caused by Trojan activation. The proposed solutions are low overhead and also generalizable to many other sensing modalities and problem instances. Simulation results using state-of-the-art tools on publicly available Trojan benchmarks verify that our approaches can detect Trojans quickly and with few false positives. Physically Unclonable Functions (PUFs) are circuits that rely on IC fabrication variations to generate unique signatures for various security applications such as IC authentication, anti-counterfeiting, cryptographic key generation, and tamper resistance. While the existence of variations has been well exploited in PUF design, knowledge of exactly how variations come into existence has largely been ignored. Yet, for several decades the Design-for-Manufacturability (DFM) community has actually investigated the fundamental sources of these variations. Furthermore, since manufacturing variations are often harmful to IC yield, the existing DFM tools have been geared towards suppressing them (counter-intuitive for PUFs). In this dissertation, we make several improvements over current state-of-the-art work in PUFs. First, our approaches exploit existing DFM models to improve PUFs at physical layout and mask generation levels. Second, our proposed algorithms reverse the role of standard DFM tools and extend them towards improving PUF quality without harming non-PUF portions of the IC. Finally, since our approaches occur after design and before fabrication, they are applicable to all types of PUFs and have little overhead in terms of area, power, etc. The innovative and unconventional techniques presented in this dissertation should act as important building blocks for future work in cyber security

Materials and processes for advanced lithography applications

textStep and Flash Imprint Lithography (S-FIL) is a high resolution, next-generation lithography technique that uses an ambient temperature and low pressure process to replicate high resolution images in a UV-curable liquid material. Application of the S-FIL process in conjunction with multi-level imprint templates and new imprint materials enables one S-FIL step to reproduce the same structures that require two photolithography steps, thereby greatly reducing the number of patterning steps required for the copper, dual damascene process used to fabricate interconnect wirings in modern integrated circuits. Two approaches were explored for the implementation of S-FIL in the dual damascene process: sacrificial imprint materials and imprintable dielectric materials. Sacrificial imprint materials function as a pattern recording medium during S-FIL and a three-dimensional etch mask during the dielectric substrate etch, enabling the simultaneous patterning of both the via and metal structures in the dielectric substrate. Development of sacrificial imprint materials and the associated imprint and etch processes are described. Application of S-FIL and the sacrificial imprint material in a commercial copper dual damascene process successfully produced functional copper interconnect structures, demonstrating the feasibility of integrating multi-level S-FIL in the copper dual damascene process. Imprintable dielectric materials are designed to combine the multi-level patterning capability of S-FIL with novel dielectric precursor materials, enabling the simultaneous deposition and patterning of the interlayer dielectric material. Several candidate imprintable dielectric materials were evaluated: sol-gel, polyhedral oligomeric silsesquioxane (POSS) epoxide, POSS acrylate, POSS azide, and POSS thiol. POSS thiol shows the most promise as functional imprintable dielectric material, although additional work in the POSS thiol formulation and viscous dispense process are needed to produce functional interconnect structures. Integration of S-FIL with imprintable dielectric materials would enable further streamlining of the dual damascene fabrication process. The fabrication of electronic devices on flexible substrates represents an opportunity for the development of macroelectronics such as flexible displays and large area devices. Traditional optical lithography encounters alignment and overlay limitations when applied on flexible substrates. A thermally activated, dual-tone photoresist system and its associated etch process were developed to enable the simultaneous patterning of two device layers on a flexible substrate.Chemical Engineerin

Near field scanning luminescence and photothermal microscopy

A near field optical scanning probe microscope with force regulation is presented. The microscope force regulation uses a differential interferometer for monitoring the tip frequency while the tip provides a sub-wavelength aperture providing a system which simultaneously records topographical information (by the force microscope) and an optical image. The flexibility of the system is evident in the specific applications pursued in this research. Simultaneous force and luminescence images derived from the investigation of porous silicon are presented. We observed variation in luminescence over sub-micron distances. Furthermore, variation in the spectral distribution of small particles of porous silicon was also observed. Both these results support the quantum wire theory proposed to explain the luminescence properties of the porous silicon and its formation. The same system was slightly reconfigured to provide imaging of thermal properties of microcircuitry. The imaging was performed by detecting changes in reflectivity as a function of temperature. The first near field photothermal probe microscope is demostrated along with a simultaneous scanning force microscope. The system shows high resolution of thermal signal, but needs some noise reduction techniques to improve image quality

Investigation of single crystal ferrite thin films

Materials suitable for use in magnetic bubble domain memories were developed for aerospace applications. Practical techniques for the preparation of such materials in forms required for fabrication of computer memory devices were considered. The materials studied were epitaxial films of various compositions of the gallium-substituted yttrium gadolinium iron garnet system. The major emphasis was to determine their bubble properties and the conditions necessary for growing uncracked, high quality films

Anti-reflection coating characterization using scattered polarized light

An increase of the energy conversion efficiency of solar cells can be achieved by minimizing reflection losses. A thin film coating serves this purpose when using optimum values of its refractive index and thickness. Also, the presence of surface roughness decreases the reflection of sunlight. Consequently, advanced cell concepts combine thin films with surface texturing. Research and development of these concepts require characterization methods. Ellipsometry is a fast, non-destructive, optical measurement diagnostic which enables characterization of substrates and films with high precision. The use of ellipsometry as characterization tool requires an optical model to extract physical information from the measured data. The optical models used for thin film metrology are generally based on flat surface samples. This work explores the possibilities to extend the range of applicability of ellipsometry to rough surface samples. Polished, acid etched and alkali etched silicon samples were deposited with thin silicon nitride films using a DEPx plasma enhanced chemical vapor deposition system which makes use of the expanding thermal plasma technique. The samples were studied by means of reflectometry, scanning electron microscopy and atomic force microscopy. A single wavelength ellipsometer (?=632.8 nm) was used to measure all samples resulting in ellipsometric layer thickness trajectories for each type of surface roughness. Comparison of the layer thickness trajectories indicated the influence of surface roughness on ellipsometry. Experiments and simulations showed that this influence can be attributed to light scattering and depolarization effects. These effects can be reduced by increasing the angle of incidence during the ellipsometry measurements.The influence of the acid etched surface roughness on the ellipsometry output showed similarities with the influence of an angle of incidence offset. A physical explanation of this behavior is given based on a feature size of the surface roughness in the so called short wavelength regime. This behavior can be exploited for relative layer characterizing measurements on deposited acid etched samples in which a film free sample is measured for reference. The accuracy of these results is acceptable for layer thickness determination, but unacceptable for the determination of the refractive index of the layer. The influence of the surface roughness of the alkali etched wafers on ellipsometry can be explained using the effective gradient medium approximation in addition to the 'angle of incidence offset' model. This extension of the effective medium approximation is designed for the long wavelength regime. It is shown that ellipsometry can be applied to rough surface samples. The influence of the surface roughness on ellipsometry can be explained physically. Additionally, ellipsometry can be used to characterize thin films on top of rough surface samples within the short wavelength regime. An increase of the energy conversion efficiency of solar cells can be achieved by minimizing reflection losses. A thin film coating serves this purpose when using optimum values of its refractive index and thickness. Also, the presence of surface roughness decreases the reflection of sunlight. Consequently, advanced cell concepts combine thin films with surface texturing. Research and development of these concepts require characterization methods. Ellipsometry is a fast, non-destructive, optical measurement diagnostic which enables characterization of substrates and films with high precision. The use of ellipsometry as characterization tool requires an optical model to extract physical information from the measured data. The optical models used for thin film metrology are generally based on flat surface samples. This work explores the possibilities to extend the range of applicability of ellipsometry to rough surface samples. Polished, acid etched and alkali etched silicon samples were deposited with thin silicon nitride films using a DEPx plasma enhanced chemical vapor deposition system which makes use of the expanding thermal plasma technique. The samples were studied by means of reflectometry, scanning electron microscopy and atomic force microscopy. A single wavelength ellipsometer (?=632.8 nm) was used to measure all samples resulting in ellipsometric layer thickness trajectories for each type of surface roughness. Comparison of the layer thickness trajectories indicated the influence of surface roughness on ellipsometry. Experiments and simulations showed that this influence can be attributed to light scattering and depolarization effects. These effects can be reduced by increasing the angle of incidence during the ellipsometry measurements.The influence of the acid etched surface roughness on the ellipsometry output showed similarities with the influence of an angle of incidence offset. A physical explanation of this behavior is given based on a feature size of the surface roughness in the so called short wavelength regime. This behavior can be exploited for relative layer characterizing measurements on deposited acid etched samples in which a film free sample is measured for reference. The accuracy of these results is acceptable for layer thickness determination, but unacceptable for the determination of the refractive index of the layer. The influence of the surface roughness of the alkali etched wafers on ellipsometry can be explained using the effective gradient medium approximation in addition to the 'angle of incidence offset' model. This extension of the effective medium approximation is designed for the long wavelength regime. It is shown that ellipsometry can be applied to rough surface samples. The influence of the surface roughness on ellipsometry can be explained physically. Additionally, ellipsometry can be used to characterize thin films on top of rough surface samples within the short wavelength regime