Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges

Terahertz (THz) communication is considered a viable approach to augmenting the communication capacity of prospective Internet-of-Things (IoT) resulting in enhanced spectral efficiency. This study first provides an outline of the design challenges encountered in developing THz transceivers. This paper introduces advanced approaches and a unique methodology known as Modified Pulse-width Modulation (MPWM) to address the issues in the THz domain. In this situation involving a transceiver that handles complex modulation schemes, the presence of a mixed signal through a high-resolution digital-to-analog converter (DAC) in the transmitter greatly contributes to the limitation in maintaining linearity at high frequencies. The utilization of Pulse-width Modulation-based Digital-to-Analog Converters (PWM-DACs) has garnered significant attention among scholars due to its efficiency and affordability. However, the converters' performance is restricted by insufficient conversion speed and precision, especially in the context of high-resolution, high-order modulation schemes for THz wireless communications. The MPWM framework offers a multitude of adjustable options, rendering the final MPWM-DAC highly adaptable for a diverse array of application scenarios. Comparative performance assessments indicate that MPWM-DACs have enhanced conversion speed compared to standard PWM-DACs, and they also provide greater accuracy in comparison to Pulse-count Modulation DACs (PCM-DACs). The study presents a comprehensive examination of the core principles, spectrum characteristics, and evaluation metrics, as well as the development and experimental validation of the MPWM method. Furthermore, we present a RISC-V System-on-Chip (SoC) that incorporates an MPWM-DAC, offering a highly favorable resolution for THz IoT communications.Comment: 18 pages, 17 figures, journa

NASA SBIR abstracts of 1992, phase 1 projects

The objectives of 346 projects placed under contract by the Small Business Innovation Research (SBIR) program of the National Aeronautics and Space Administration (NASA) are described. These projects were selected competitively from among proposals submitted to NASA in response to the 1992 SBIR Program Solicitation. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 346, in order of its appearance in the body of the report. Appendixes to provide additional information about the SBIR program and permit cross-reference of the 1992 Phase 1 projects by company name, location by state, principal investigator, NASA Field Center responsible for management of each project, and NASA contract number are included

Um amplificador de transcondutância cmos de baixa potência com melhoria da cmrr

This work presents a topology of a low power Transconductance Operational Amplifier (OTA) for the compensation of Common Mode Rejection Ratio (CMRR), in which the transistors operate in the strong inversion mode. Initially, a theoretical review of the differential amplifier and OTA is presented. Then, an OTA architecture was proposed based on a symmetric differential amplifier structure with additional transistors in parallel to the input MOS transistors, in order to increase the CMRR rate, as well as the proposed compensation strategy. The OTA was designed using IBM 130 nm CMOS technology. Monte Carlo and Corner simulations were performed to analyze the compensation strategy and to obtain a more realistic assessment. The results obtained demonstrate that the proposed circuit for common mode control operates correctly, since the proposed OTA enabled common mode control in parallel, obtaining a CMRR of 87.34 dB and power consumption of 9.65 μW, validating its compatibility with low power circuits.Agência 1Este trabalho apresenta uma topologia de um Amplificador Operacional de Transcondutância (OTA) de baixa potência para a compensação da Razão de Rejeição de Modo Comum (CMRR), onde os transistores operam no modo de inversão forte. Inicialmente, é apresentada uma revisão teórica acerca do amplificador diferencial e do OTA. Em seguida, foi proposta uma arquitetura de OTA baseado em uma estrutura de amplificador diferencial simétrico com transistores adicionais em paralelo aos transistores MOS de entrada, a fim de aumentar a taxa de CMRR, bem como a estratégia de compensação proposta. O OTA foi projetado utilizando a tecnologia CMOS IBM 130 nm. Para analisar a estratégia de compensação e obter uma avaliação mais realista foram realizadas as simulações de Monte Carlo e Corner. Os resultados obtidos demonstram que o circuito proposto para controle de modo comum opera corretamente, uma vez que o OTA proposto possibilitou o controle de modo comum em paralelo obtendo uma CMRR de 87,34 dB e consumo de potência de 9,65 μW, validando sua compatibilidade com circuitos de baixa potência

Reconfigurable Antenna Systems: Platform implementation and low-power matters

Antennas are a necessary and often critical component of all wireless systems, of which they share the ever-increasing complexity and the challenges of present and emerging trends. 5G, massive low-orbit satellite architectures (e.g. OneWeb), industry 4.0, Internet of Things (IoT), satcom on-the-move, Advanced Driver Assistance Systems (ADAS) and Autonomous Vehicles, all call for highly flexible systems, and antenna reconfigurability is an enabling part of these advances. The terminal segment is particularly crucial in this sense, encompassing both very compact antennas or low-profile antennas, all with various adaptability/reconfigurability requirements. This thesis work has dealt with hardware implementation issues of Radio Frequency (RF) antenna reconfigurability, and in particular with low-power General Purpose Platforms (GPP); the work has encompassed Software Defined Radio (SDR) implementation, as well as embedded low-power platforms (in particular on STM32 Nucleo family of micro-controller). The hardware-software platform work has been complemented with design and fabrication of reconfigurable antennas in standard technology, and the resulting systems tested. The selected antenna technology was antenna array with continuously steerable beam, controlled by voltage-driven phase shifting circuits. Applications included notably Wireless Sensor Network (WSN) deployed in the Italian scientific mission in Antarctica, in a traffic-monitoring case study (EU H2020 project), and into an innovative Global Navigation Satellite Systems (GNSS) antenna concept (patent application submitted). The SDR implementation focused on a low-cost and low-power Software-defined radio open-source platform with IEEE 802.11 a/g/p wireless communication capability. In a second embodiment, the flexibility of the SDR paradigm has been traded off to avoid the power consumption associated to the relevant operating system. Application field of reconfigurable antenna is, however, not limited to a better management of the energy consumption. The analysis has also been extended to satellites positioning application. A novel beamforming method has presented demonstrating improvements in the quality of signals received from satellites. Regarding those who deal with positioning algorithms, this advancement help improving precision on the estimated position

Continuous-time analog circuits for statistical signal processing

Thesis (Ph. D.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2003.Vita.Includes bibliographical references (p. 205-209).This thesis proposes an alternate paradigm for designing computers using continuous-time analog circuits. Digital computation sacrifices continuous degrees of freedom. A principled approach to recovering them is to view analog circuits as propagating probabilities in a message passing algorithm. Within this framework, analog continuous-time circuits can perform robust, programmable, high-speed, low-power, cost-effective, statistical signal processing. This methodology will have broad application to systems which can benefit from low-power, high-speed signal processing and offers the possibility of adaptable/programmable high-speed circuitry at frequencies where digital circuitry would be cost and power prohibitive. Many problems must be solved before the new design methodology can be shown to be useful in practice: Continuous-time signal processing is not well understood. Analog computational circuits known as "soft-gates" have been previously proposed, but a complementary set of analog memory circuits is still lacking. Analog circuits are usually tunable, rarely reconfigurable, but never programmable. The thesis develops an understanding of the convergence and synchronization of statistical signal processing algorithms in continuous time, and explores the use of linear and nonlinear circuits for analog memory. An exemplary embodiment called the Noise Lock Loop (NLL) using these design primitives is demonstrated to perform direct-sequence spread-spectrum acquisition and tracking functionality and promises order-of-magnitude wins over digital implementations. A building block for the construction of programmable analog gate arrays, the "soft-multiplexer" is also proposed.by Benjamin Vigoda.Ph.D