4,248 research outputs found
Neuro-memristive Circuits for Edge Computing: A review
The volume, veracity, variability, and velocity of data produced from the
ever-increasing network of sensors connected to Internet pose challenges for
power management, scalability, and sustainability of cloud computing
infrastructure. Increasing the data processing capability of edge computing
devices at lower power requirements can reduce several overheads for cloud
computing solutions. This paper provides the review of neuromorphic
CMOS-memristive architectures that can be integrated into edge computing
devices. We discuss why the neuromorphic architectures are useful for edge
devices and show the advantages, drawbacks and open problems in the field of
neuro-memristive circuits for edge computing
A Compact CMOS Memristor Emulator Circuit and its Applications
Conceptual memristors have recently gathered wider interest due to their
diverse application in non-von Neumann computing, machine learning,
neuromorphic computing, and chaotic circuits. We introduce a compact CMOS
circuit that emulates idealized memristor characteristics and can bridge the
gap between concepts to chip-scale realization by transcending device
challenges. The CMOS memristor circuit embodies a two-terminal variable
resistor whose resistance is controlled by the voltage applied across its
terminals. The memristor 'state' is held in a capacitor that controls the
resistor value. This work presents the design and simulation of the memristor
emulation circuit, and applies it to a memcomputing application of maze solving
using analog parallelism. Furthermore, the memristor emulator circuit can be
designed and fabricated using standard commercial CMOS technologies and opens
doors to interesting applications in neuromorphic and machine learning
circuits.Comment: Submitted to International Symposium of Circuits and Systems (ISCAS)
201
Curvature of BEOL cantilevers in CMOS-MEMS processes
© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents the curvature characterization results of released back-end-of-line 5 µm-wide cantilevers for two different 0.18-µm 1P6M complementary metal-oxide semiconductor microelectromechanical systems processes. Results from different runs and lots from each foundry are presented. The methodology and accuracy of the characterization approach, based on optical measurements of test cantilever curvature, are also discussed. Special emphasis is given to the curvature average and variability as a function of the number of stacked layers. Analythical equations for modeling the bending behavior of stacked cantilevers as a function of the tungsten (W) vias that join the metal layers are presented. In addition, the effect of various post-processing conditions and design techniques on the curvature of both single and stacked cantilevers is analyzed. In particular, surpassing certain time-dependent temperature stress conditions after release lead to curvature shifts larger than one order of magnitude. Also, the W via design was found to strongly affect the curvature of the test cantilevers.Peer ReviewedPostprint (author's final draft
Grid infrastructures for the electronics domain: requirements and early prototypes from an EPSRC pilot project
The fundamental challenges facing future electronics design is to address the decreasing – atomistic - scale of transistor devices and to understand and predict the impact and statistical variability these have on design of circuits and systems. The EPSRC pilot project “Meeting the Design Challenges of nanoCMOS Electronics” (nanoCMOS) which began in October 2006 has been funded to explore this space. This paper outlines the key requirements that need to be addressed for Grid technology to support the various research strands in this domain, and shows early prototypes demonstrating how these requirements are being addressed
Quantifying Near-Threshold CMOS Circuit Robustness
In order to build energy efficient digital CMOS circuits, the supply voltage must be reduced to near-threshold.
Problematically, due to random parameter variation, supply
scaling reduces circuit robustness to noise. Moreover, the effects of parameter variation worsen as device dimensions diminish, further reducing robustness, and making parameter variation one of the most significant hurdles to continued CMOS scaling. This paper presents a new metric to quantify circuit robustness with respect to variation and noise along with an efficient method of calculation. The method relies on the statistical analysis of standard cells and memories resulting an an extremely compact representation of robustness data. With this metric and method of
calculation, circuit robustness can be included alongside energy, delay, and area during circuit design and optimization
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
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