Analysis and modeling of underfill flow driven by capillary action in flip-chip packaging

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance

On the Use of Self-Assembling Block Copolymers to Toughen A Model Epoxy

Block copolymers have been receiving considerable attention in tougheningepoxy due to their ability to form a wide variety of nanostructures. This study focuseson using both triblock and diblock copolymers to improve the fracture toughness ofan aromatic-amine cured epoxy system. The curing system consisted of 1,3-phenylenediamine (mPDA) as curing agent and aniline as a chain extender. Threetriblock copolymers and three diblock copolymers were incorporated in the samelightly crosslinked model epoxy system, which was chosen to mimic an underfillmaterial in flip-chip packaging for the microelectronics industry.In this research, rubber particles were formed in situ using self-assembling blockcopolymers. Mechanical, thermal and microscopic studies were conducted with themain goal to study the relationship between the block parameters and the finalmorphologies and their effects on static and dynamic mechanical properties of thetoughened resin, especially fracture toughness.In these block-copolymer-modified epoxies, spherical micelles and wormlikemicelles were obtained by varying block lengths, molecular weight, polarities andcompositions. It was found that miscibility of the epoxy-miscible block played acrucial role in the formation of different types of morphologies. At a low loadinglevel, diblock copolymers were able to toughen the model epoxy as effectively astriblock copolymers. The fracture toughness was improved to almost three times withrespect to that of the neat resin with addition of 10 phr AM*-27. At the same time,other mechanical properties, such as yield strength and modulus, were well retained.Incorporation of block copolymers did not have a significant effect on glass transitiontemperature but caused an increase in coefficient of thermal expansion (CTE) of themodified epoxy. Particle cavitation and matrix void growth were proved to be thetoughening mechanisms for SBM-Modified epoxies. However, these typicaltoughening mechanisms for rubber toughening were not identified in the AM*27-modified epoxies by examining the fracture surface and the subsurface damage

The Development of Novel Interconnection Technologies for 3D Packaging of Wire Bondless Silicon Carbide Power Modules

This dissertation advances the cause for the 3D packaging and integration of silicon carbide power modules. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were investigated, and the concept for a novel SiC power module was discussed. This highly-integrated SiC power module was assessed for feasibility, with a focus on achieving ultralow parasitic inductances in the critical switching loops. This will enable higher switching frequencies, leading to a reduction in the size of the passive devices in the system and resulting in systems with lower weight and volume. The proposed concept yielded an order-of-magnitude reduction in system parasitics, alongside the possibility of a compact system integration. The technological barriers to realizing these concepts were identified, and solutions for novel interconnection schemes were proposed and evaluated. A novel sintered silver preform was developed to facilitate flip-chip interconnections for a bare-die power device while operating in a high ambient temperature. The preform was demonstrated to have 3.75× more bonding strength than a conventional sintered silver bond and passed rigorous thermal shock tests. A chip-scale and flip-chip capable power device was also developed. The novel package combined the ease of assembly of a discrete device with a performance exceeding a wire bonded module. It occupied a 14× smaller footprint than a discrete device, and offered power loop inductances which were less than a third of a conventional wire bonded module. A detailed manufacturing process flow and qualification is included in this dissertation. These novel devices were implemented in various electrical systems—a discrete Schottky barrier diode package, a half-bridge module with external gate drive, and finally a half-bridge with integrated gate driver in-module. The results of these investigations have been reported and their benefits assessed. The wire bondless modules showed \u3c 5% overshoot under all test conditions. No observable detrimental effects due to dv/dt were observed for any of the modules even under aggressive voltage slew rates of 20-25 V/ns

Digitally driven microfabrication of 3D multilayer embedded electronic systems

The integration of multiple digitally driven processes is seen as the solution to many of the current limitations arising from standalone Additive Manufacturing (AM) techniques. A technique has been developed to digitally fabricate fully functioning electronics using a unique combination of AM technologies. This has been achieved by interleaving bottom-up Stereolithography (SL) with Direct Writing (DW) of conductor materials alongside mid-process development (optimising the substrate surface quality), dispensing of interconnects, component placement and thermal curing stages. The resulting process enables the low-temperature production of bespoke three-dimensional, fully packaged and assembled multi-layer embedded electronic circuitry. Two different Digital Light Processing (DLP) Stereolithography systems were developed applying different projection orientations to fabricate electronic substrates by selective photopolymerisation. The bottom up projection orientation produced higher quality more planar surfaces and demonstrated both a theoretical and practical feature resolution of 110 μm. A top down projection method was also developed however a uniform exposure of UV light and planar substrate surface of high quality could not be achieved. The most advantageous combination of three post processing techniques to optimise the substrate surface quality for subsequent conductor deposition was determined and defined as a mid-processing procedure. These techniques included ultrasonic agitation in solvent, thermal baking and additional ultraviolet exposure. SEM and surface analysis showed that a sequence including ultrasonic agitation in D-Limonene with additional UV exposure was optimal. DW of a silver conductive epoxy was used to print conductors on the photopolymer surface using a Musashi dispensing system that applies a pneumatic pressure to a loaded syringe mounted on a 3-axis print head and is controlled through CAD generated machine code. The dispensing behaviour of two isotropic conductive adhesives was characterised through three different nozzle sizes for the production of conductor traces as small as 170 μm wide and 40 μm high. Additionally, the high resolution dispensing of a viscous isotropic conductive adhesive (ICA) also led to a novel deposition approach for producing three dimensional, z-axis connections in the form of high freestanding pillars with an aspect ratio of 3.68 (height of 2mm and diameter of 550μm). Three conductive adhesive curing regimes were applied to printed samples to determine the effect of curing temperature and time on the resulting material resistivity. A temperature of 80 °C for 3 hours resulted in the lowest resistivity while displaying no substrate degradation. ii Compatibility with surface mount technology enabled components including resistors, capacitors and chip packages to be placed directly onto the silver adhesive contact pads before low-temperature thermal curing and embedding within additional layers of photopolymer. Packaging of components as small as 0603 surface mount devices (SMDs) was demonstrated via this process. After embedding of the circuitry in a thick layer of photopolymer using the bottom up Stereolithography apparatus, analysis of the adhesive strength at the boundary between the base substrate and embedding layer was conducted showing that loads up to 1500 N could be applied perpendicular to the embedding plane. A high degree of planarization was also found during evaluation of the embedding stage that resulted in an excellent surface finish on which to deposit subsequent layers. This complete procedure could be repeated numerous times to fabricate multilayer electronic devices. This hybrid process was also adapted to conduct flip-chip packaging of bare die with 195 μm wide bond pads. The SL/DW process combination was used to create conductive trenches in the substrate surface that were filled with isotropic conductive adhesive (ICA) to create conductive pathways. Additional experimentation with the dispensing parameters led to consistent 150 μm ICA bumps at a 457 μm pitch. A flip-chip bonding force of 0.08 N resulted in a contact resistance of 2.3 Ω at a standoff height of ~80 μm. Flip-chips with greater standoff heights of 160 μm were also successfully underfilled with liquid photopolymer using the SL embedding technique, while the same process on chips with 80 μm standoff height was unsuccessful. Finally the approaches were combined to fabricate single, double and triple layer circuit demonstrators; pyramid shaped electronic packages with internal multilayer electronics; fully packaged and underfilled flip-chip bare die and; a microfluidic device facilitating UV catalysis. This new paradigm in manufacturing supports rapid iterative product development and mass customisation of electronics for a specific application and, allows the generation of more dimensionally complex products with increased functionality

Investigation into Solder Joint Failure in Portable Electronics Subjected to Drop Impact

Ph.DDOCTOR OF PHILOSOPH

Piin läpivientien luotettavuus ja elinikä termisessä rasituksessa

Through-silicon via (TSV) is one of the key technologies for three-dimensional (3D) integrated circuits (ICs). TSVs enable vertical electrical connections between components which greatly reduces interconnection lengths. Regardless of all the promise the technique has shown, there are still major obstacles surrounding reliability and the cost of fabrication of the TSV structure. The first part of the thesis is a literature survey that focuses on different failure mechanisms of TSVs. In addition, different fabrication and design choices of TSVs are presented with the focus being on their effect on reliability. The experimental part of the thesis presents reliability and lifetime assessment of tapered partially copper-filled blind TSVs under thermal cycling. The reliability test was carried out with nine samples. Six of them had 420 vias and three of them had 1400 vias in a daisy chain structure. Finite element method (FEM) was used to predict the critical failure locations of the TSV structure. Lifetime was predicted by Weibull analysis. The cross-sections of the test samples were prepared by molding, mechanical grinding and polishing and analyzed by scanning electron microscope (SEM). Electrical measurements showed almost constant resistance increase in the samples before failures were noticed. The first failed sample was noticed after 200 cycles and the last at 4000 cycles. Lifetime of TSVs under thermal cycling was proven to be acceptable with used failure criterion. According to Weibull analysis, about 10 % of the samples with 420 vias will break after 1000 cycles. Sample preparation for imaging was deemed sufficient although the grinding caused artifacts. The simulation results were compared with SEM micrographs. The images showed that the failures were located at the maximum stress areas, identified with FEM simulations, at the bottom of the via. From the SEM images, it was deduced that the defects initiated from the fabrication process and propagated due to maximum localized stress.Piin läpivienti -rakenteet ovat keskeisessä osassa kolmiulotteisten integroitujen piirien kehityksessä. Piin läpiviennit mahdollistavat komponenttien vertikaalin yhdistämisen toisiinsa, mikä lyhentää huomattavasti niiden välistä etäisyyttä. Kaikista hyvistä puolista huolimatta tekniikalla on vielä haasteita edessään. Niistä suurimmat liittyvät rakenteen luotettavuuteen ja valmistuskustannuksiin. Diplomityön kirjallisessa osuudessa keskitytään piin läpivientien erilaisiin vauriomekanismeihin. Sen lisäksi tutkitaan valmistus- ja suunnitteluratkaisujen vaikutusta läpivientien luotettavuuteen. Kokeellisen osan tarkoituksena on osittain kuparitäytettyjen kaventuvien piin läpivientien luotettavuuden ja eliniän määrittäminen termisessä syklaustestissä. Luotettavuustestaus suoritettiin yhdeksällä näytteellä, joista kuudessa oli 420 läpivientiä ja kolmessa 1400 läpivientiä ketjurakenteessa. Elementtimallintamisen avulla määritettiin kriittiset vauriokohdat läpivientirakenteessa ja elinikä määritettiin Weibull-analyysillä. Näytteiden poikkileikkauksien valmistamiseen käytettiin muovaamista, mekaanista hiomista ja kiillotusta ja analysointi suoritettiin pyyhkäisyelektronimikroskoopilla. Näytteiden resistanssi nousi tasaisesti ennen rikkoutumisten havaitsemista. Ensimmäinen rikkoutuminen huomattiin 200 syklin jälkeen ja viimeinen 4000 syklin kohdalla. Näytteiden luotettavuus osoittautui hyväksi käytetyillä kriteereillä. Weibull-analyysin mukaan 10 % 420 läpiviennin näytteistä rikkoutuu 1000 syklin jälkeen. Karkea arvio voidaan tehdä, että satunnainen läpivienti rikkoutuu 0,024 % todennäköisyydellä 1000 syklin jälkeen. Pyyhkäisyelektronimikroskoopin kuvien perusteella havaittiin, että näytteet rikkoutuivat maksimaalisen rasituksen alueella läpivientien alaosassa. Kuvien perusteella päädyttiin johtopäätökseen, että näytteiden rikkoutumisen aiheuttivat virheet, jotka ovat peräisin valmistusprosessista ja jotka etenivät rakenteessa termisen rasituksen vaikutuksesta

Compliant copper microwire arrays for reliable interconnections between large low-CTE packages and printed wiring board

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.Ph.D

Design and Manufacture of Molding Compounds for High Reliability Microelectronics in Extreme Conditions

The widespread use of electronics in more avenues of consumer use is increasing. Applications range from medical instrumentation that directly can affect someone's life, down hole sensors for oil and gas, aerospace, aeronautics, and automotive electronics. The increased power density and harsh environment makes the reliability of the packaging a vital part of the reliability of the device. The increased importance of analog devices in these applications, their high voltage and high temperature resilience is resulting in challenges that have not been dealt with before. In particular packaging where insulative properties are vital use polymer resins modified by ceramic fillers. The distinct dielectric properties of the resin and the filler result in charge storage and release of the polarization currents in the composite that have had unpredictable consequences on reliability. The objective of this effort is therefore to investigate a technique that can be used to measure the polarization in filled polymer resins and evaluate reliable molding compounds. A valuable approach to measure polarization in polymers where charge release is tied to the glass transition in the polymer is referred to as thermally stimulated depolarization current (TSDC) technique. In this dissertation a new TSDC measurement system was designed and fabricated. The instrument is an assembly of several components that are automated via a LabVIEW program that gives the user flexibility to test different dielectric compounds at high temperatures and high voltage. The temperature control is enabled through the use of dry air convection heating at a very slow rate enabling controlled heating and cooling. Charge trapping and de-trapping processes were investigated in order to obtain information on insulating polymeric composites and how to optimize it. A number of material properties were investigated. First, polarization due to charges on the filer were investigated using composites containing charged and uncharged particles using quartz and ion exchange montmorillonite silicates in an epoxy matrix. The thermally-activated charge release shows a difference in the composite characteristics and preparation. This difference indicates that the trap levels depend on the de-trapping process and on the chemical nature of the trap site. Using a numerical approach to the release spectra, a model was developed to examine through short time testing, important parameters such as glass transition temperature, residual polarization, depolarization peak, window polarization modeling and activation energy of relaxations. Second the design of mold compounds that could combine manufacturing (temperature of molding), geometric (thickness of packaging material), composition (amount and size of filler) effects was developed using a novel design of experiments approach. The statistical DOE enabled the determination of which causes should be considered when designing a mold compound that has minimal polarization both as singular variables as well as combined variables. Finally, the DOE approach was used to develop a high temperature reliable molding compound through use of combined fillers of thermally conductive and nonconductive fillers having different shapes. Through the systematic approach to developing a technique and designing a mold compound addressing the multiple impacts on reliability of packaging, the dissertation provides an approach to the design, selection, performance and durability of molding compounds

Preparation and Characterization of Calcium Copper Titanate Filled Epoxy Composites for Embedded Capacitor Applications

Permintaan yang semakin meningkat untuk pengecilan peranti elektronik menawarkan pengurangan saiz yang ketara, prestasi dielektrik dan haba yang lebih baik, kebolehpercayaan dan kos yang lebih rendah. Komposit polimer-seramik telah dipilih sebagai bahan dielektrik yang paling sesuai untuk kapasitor terbenam. Dalam kajian ini, seramik seperti kalsium kuprum titanat, CaCu3Ti4O12 (CCTO) dan barium titanat (BaTiO3) telah digunakan sebagai pengisi dalam komposit epoksi filem nipis. Sifat-sifat komposit epoksi filem nipis dihasilkan berdasarkan muatan pengisi yang berbeza (5 hingga 20% isipadu), kaedah fabrikasi seperti salutan putaran (SC) dan tekan panas (HP), pengisi hibrid (CCTO dan BaTiO3), rawatan permukaan pengisi dan pelbagai jenis resin epoksi (DER 332, Epolam 2015 dan OP 392) telah dikaji. Keputusan menunjukkan bahawa komposit CCTO/epoksi mempamerkan pemalar dielektrik, Tg dan kekonduksian haba yang lebih tinggi berbanding dengan epoksi tidak terisi dan komposit BaTiO3/epoksi. Dalam siri kedua, pengisi CCTO untuk pengisian komposit epoksi telah dipilih untuk siasatan lanjutan. Komposit CCTO/epoksi dengan pengisian sehingga 40% isipadu dapat dihasilkan dengan menggunakan kaedah HP. Hasil ujian telah menunjukkan bahawa sifat-sifat komposit 40% isipadu CCTO/epoksi (HP) telah meningkat sebanyak 55% pemalar dielektrik dan 83% modulus simpanan, dan penurunan 69% pekali pengembangan haba berbanding dengan sifat-sifat komposit 20% isipadu CCTO/epoksi (SC). Pengisi Hibrid untuk pengisian komposit epoksi telah dihasilkan dan keputusan menunjukkan bahawa Hibrid 70:30 mempamerkan kesan hibrid yang positif berbanding dengan komposit pengisi tunggal; komposit filem nipis CCTO/epoksi dan BaTiO3/epoksi. Selepas rawatan CCTO oleh ejen gandingan silana, sampel komposit epoksi terisi CCTO 10% yang terawat menunjukkan peningkatan yang memberangsangkan iaitu sebanyak 60% pemalar dielektrik berbanding komposit filem nipis CCTO/epoksi yang tidak terawat. Berdasarkan pelbagai resin epoksi, komposit filem nipis CCTO/epoksi OP 392 yang terawat mempamerkan kenaikan pemalar dielektrik sebanyak 10% dan susutan dalam pekali pengembangan haba sebanyak 38% berbanding dengan bahan dielektrik komersial, iaitu 3M Embedded Capacitor. Secara kesimpulannya, komposit filem nipis CCTO/epoksi OP 392 yang terawat menunjukkan prestasi yang baik dari segi pemalar dielektrik dan haba berbanding komposit CCTO yang tidak terawat, komposit hibrid dan lain-lain komposit terawat. ________________________________________________________________________________________________________________________ Continuous miniaturization of electronic devices result in a high demand of embedded capacitor that offers significant reduction in size, better dielectric and thermal performance, reliability and lower cost. Polymer-ceramic composites have been considered as the most suitable dielectric materials for embedded capacitor. In this study, ceramics such as calcium copper titanate, CaCu3Ti4O12 (CCTO) and barium titanate (BaTiO3) were used as fillers in epoxy thin film composites. The properties of epoxy thin film composites fabricated based on different filler loading (5 to 20 vol%), fabrication methods such as spin coating (SC) and hot press (HP) methods, hybrid fillers (CCTO and BaTiO3), surface treatment of filler and various types of epoxy resins (DER 332, Epolam 2015 and OP 392) were characterized. Results showed that CCTO/epoxy composite exhibited higher dielectric constant, Tg and thermal conductivity compared to those of unfilled epoxy and BaTiO3/epoxy composites. In the second series, CCTO filler filled epoxy composite was chosen for further investigation. CCTO/epoxy composite with filler loading of up to 40 vol% was able to be produced by using HP method. It was found that 40 vol% CCTO/epoxy (HP) composite has increased 55% of dielectric constant and 83% of storage modulus, and decreased 69% of CTE compared to 20 vol% CCTO/epoxy (SC) composite. Hybrid fillers composites were fabricated and results indicated that Hybrid 70:30 showed positive hybrid effect compared to those of single filler composites; CCTO/epoxy and BaTiO3/epoxy thin film composites. After treatment of CCTO by silane-based coupling agent, sample with 10% treated CCTO filled epoxy composite presented remarkable improvement with an increased 60% of dielectric constant than untreated CCTO/epoxy thin film composite. Based on various epoxy resins, treated CCTO/OP 392 epoxy thin film composite has improved 10% of dielectric constant and decreased 38% of CTE compared to 3M Embedded Capacitor. In short, treated CCTO filled OP 392 epoxy thin film composite exhibited good dielectric properties and thermal properties compared to those of untreated CCTO composites, hybrid fillers composites and other treated composites