System-Level Analysis for Integrated Power Amplifier Design in mmWave Consumer Wireless Communications

System-level specifications for the design of integrated power amplifiers in mmWave wireless communications are derived in the paper. To this aim emerging standards for consumer applications such as wireless ultra-high definition (UHD) multimedia streaming or Gbit wireless LAN are considered (WirelessHD, WiGig, ECMA387, IEEE.802.11.ad, IEEE802.15.3c and upcoming 5G). A power amplifier design in 65 nm CMOS Silicon on Insulator (SOI) technology, targeting a 9 GHz UWB window from 57 to 66 GHz, is also proposed. To increase the power delivered to the antenna up to 18 mW, being still in the limit of maximum 1 dB compression point, multiple PA cores have been combined through a Wilkinson power combiner, but other solutions can be also explored for a better power efficiency and linearity

Real-time FPGA-based Radar Imaging for Smart Mobility Systems

The paper presents an X-band FMCW (Frequency Modulated Continuous Wave) Radar Imaging system, called X-FRI, for surveillance in smart mobility applications. X-FRI allows for detecting the presence of targets (e.g. obstacles in a railway crossing or urban road crossing, or ships in a small harbor), as well as their speed and their position. With respect to alternative solutions based on LIDAR or camera systems, X-FRI operates in real-time also in bad lighting and weather conditions, night and day. The radio-frequency transceiver is realized through COTS (Commercial Off The Shelf) components on a single-board. An FPGA-based baseband platform allows for real-time Radar image processing

VLSI design investigation for low-cost, low-power FFT/IFFT processing in advanced VDSL transceivers

The problem of an efficient very large scale integration (VLSI) realization of the direct/inverse fast Fourier transform (FFT/IFFT) for digital subscriber line (DSL) applications is addressed in this paper. The design of scalable and very high-rate (VDSL) modem claims for large and high-throughput complex FFT computations while for massive and fast deployment of the xDSL family low-cost and low-power constraints are key issues. Throughout the paper we explore the design space at different levels (algorithm, arithmetic accuracy, architecture, technology) to achieve the best trade-off between processing performance, hardware complexity and power consumption. A programmable VLSI processor based on a FFT/IFFT cascade architecture plus pre/post-processing stages is discussed and characterized from the high-level choices down to the gate-level synthesis. Furthermore low-power design techniques, based on clock gating and data driven switching activity reduction, are used to decrease the power consumption exploiting the correlation of the FFT/IFFT coefficients and the statistics of the input signals. To this aim both frequency-division and time-division duplex schemes have been considered. The effects of supply voltage scaling and its consequence on circuit performance are examined in detail, as well as the use of different target technologies. Synthesis results for a 0.18 mum CMOS standard-cells technology show that the processor is suitable for real-time modulation and demodulation in scalable full-rate VDSL modem (64-4096 complex FFT, 20 Msample/s) with a power consumption of few tens of mW. These performances are very interesting when compared to state-of-the-art software implementations and custom VLSI ones. (C) 2002 Elsevier Science Ltd. All rights reserved