Design and Analysis of 8x8 Wallace Tree Multiplier using GDI and CMOS Technology

Multiplier is a small unit of an arithmetic circuit that is widely used in Digital filters, Digital Signal Processing, microprocessors and communication applications etc. In today's scenario compact and small digital devices are critical concern in the field of VLSI design, which should perform fast as well as low power consumption. Optimizing the delay, area and power of a multiplier is a major design issues, as area and speed are usually conflicting constraints. A Wallace tree multiplier is an improved version of tree base multiplier. The main aim of this paper is a reconfigurable 8x8 Wallace Tree multiplier using CMOS and GDI technology. This is efficient in power and regularity without increase in delay and area. The generation of partial products in parallel using AND gates. The addition of partial products is reducing using Wallace Tree which is divided into levels. Therefore there will be a certain reduction in the power consumption, since power is provided only to the level that is involved in computation and the remaining two levels remain off

Design and Testing of High Speed Multipliers by using Reversible Liner Feedback Shift Register

In recent designs of IC’s (Integrated Circuits) BIST (Built-In Self-Test) is becoming vital for memory where memory is essential part of SoC (System on Chip). BIST design technique allows circuit for self testing. A technique may provide the short test-time as compared to test which applied externally and it allows a use of the low cost test instruments throughout the all production stages. Because of LFSRs randomness properties, it requires less hardware overhead. In particular dissertation, optimization and structure design of BIST design is based on the Reversible LFSRs, which are described. As well Reversible LFSR and Proposed LT LFSR are used to design and test Architecture of different Multipliers such as Array Multipliers and Booth Multiplier

FPGA Implementation & Performance Comparision of Various High Speed unsigned Binary Multipliers using VHDL

Today, most of the DSP computations involve the use of multiply accumulate operations and therefore the design of fast and efficient multipliers is imperative. The addition and multiplication of two binary numbers is the fundamental and most often used arithmetic operation in microprocessors, digital signal processors and data-processing application-specific integrated circuits. In this paper, we present the study of different types of multipliers by comparing the speed and area of each. In this work, VHDL coding and XILINX ISE Simulator is employed to implement multipliers like WTM, Dadda Multiplier, Vedic Multiplier, CSHM, Serial Multiplier and Multipliers using different compressors in Wallace tree architecture. The analysis of this work would be helpful to choose a better multiplier in order to fabricate an efficient system