Spiking ink drop spread clustering algorithm and its memristor crossbar conceptual hardware design

In this study, a novel neuro-fuzzy clustering algorithm is proposed based on spiking neural network and ink drop spread (IDS) concepts. The proposed structure is a one-layer artificial neural network with leaky integrate and fire (LIF) neurons. The structure implements the IDS algorithm as a fuzzy concept. Each training data will result in firing the corresponding input neuron and its neighboring neurons. A synchronous time coding algorithm is used to manage input and output neurons firing time. For an input data, one or several output neurons of the network will fire; confidence degree of the network to outputs is defined as the relative delay of the firing times with respect to the synchronous pulse. A memristor crossbar-based hardware is utilized for hardware implementation of the proposed algorithm. The simulation result corroborates that the proposed algorithm can be used as a neuro-fuzzy clustering and vector quantization algorithm

Memristor-Based Digital Systems Design and Architectures

Memristor is considered as a suitable alternative solution to resolve the scaling limitation of CMOS technology. In recent years, the use of memristors in circuits design has rapidly increased and attracted researcher’s interest. Advances have been made to both size and complexity of memristor designs. The development of CMOS transistors shows major concerns, such as, increased leakage power, reduced reliability, and high fabrication cost. These factors have affected chip manufacturing process and functionality severely. Therefore, the demand for new devices is increasing. Memristor, is considered as one of the key element in memory and information processing design due to its small size, long-term data storage, low power, and CMOS compatibility. The main objective in this research is to design memristor-based arithmetic circuits and to overcome some of the Memristor based logic design issues. In this thesis, a fast, low area and low power hybrid CMOS memristor based digital circuit design were implemented. Small and large-scale memristor based digital circuits are implemented and provided a solutions for overcoming the memristor degradation and fan-out challenges. As an example, a 4- bit LFSR has been implemented by using MRL scheme with 64 CMOS devices and 64 memristors. The proposed design is more efficient in terms of the area when compared with CMOS- based LFSR circuits. The simulation results proves the functionality of the design. This approach presents acceptable speed in comparison with CMOS-based design and it is faster than IMPLY-based memrisitive LFSR. The propped LFSR has 841 ps de-lay. Furthermore, the proposed design has a significant power reduction of over 66% less than CMOS-based approach. This thesis proposes implementation of memristive 2-D median filter and extends previously published works on memristive Filter design to include this emerging technology characteristics in image processing. The proposed circuit was designed based on Pt/TaOx/Ta redox-based device and Memristor Ratioed Logic (MRL). The proposed filter is designed in Cadence and the memristive median approved tested circuit is translated to Verilog-XL as a behavioral model. Different 512 _ 512 pixels input images contain salt and pepper noise with various noise density ratios are applied to the proposed median filter and the design successfully has substantially removed the noise. The implementation results in comparison with the conventional filters, it gives better Peak Signal to Noise Ratio (PSNR) and Mean Absolute Error (MAE) for different images with different noise density ratios while it saves more area as compared to CMOS-based design. This dissertation proposes a comprehensive framework for design, mapping and synthesis of large-scale memristor-CMOS circuits. This framework provides a synthesis approach that can be applied to all memristor-based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor-based logic cells to generate a standard cell library for large scale simulation. The proposed framework is implemented in the Cadence Virtuoso schematic-level environment and was veri_ed with Verilog-XL, MATLAB, and the Electronic Design Automation (EDA) Synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. The frame work is deployed for design of the memristor-based parallel 8-bit adder/subtractor and a 2-D memristive-based median filter

Bio-inspired Hardware Architectures for Memory, Image Processing, and Control Applications

Emerging technologies are expected to partially replace and enhance CMOS systems as the end of transistor scaling approaches. A particular type of emerging technology of interest is the variable resistance devices due to their scalability, non-volatile nature, and CMOS process compatibility. The goal of this dissertation is to present circuit and system level applications of CMOS and variable resistance devices with bio-inspired computation paradigms as the main focus. The summary of the results offered per chapter is as follows: In the first chapter of this thesis, an introduction to the work presented in the rest of this thesis and the model for the variable resistance device is provided. In the second chapter of this thesis, a crossbar memory architecture that utilizes a reduced constraint read-monitored-write scheme is presented. Variable resistance based crossbar memories are prime candidates to succeed the Flash as the mainstream nonvolatile memory due to their density, scalability, and write endurance. The proposed scheme supports multi-bit storage per cell and utilizes reduced hardware, aiming to decrease the feedback complexity and latency while still operating with CMOS compatible voltages. Additionally, a read technique that can successfully distinguish resistive states under the existence of resistance drift due to read/write disturbances in the array is presented. Derivations of analytical relations are provided to set forth a design methodology in selecting peripheral device parameters. In the third chapter of this thesis, an analog programmable resistive grid-based architecture mimicking the cellular connections of a biological retina in the most basic level, capable of performing various real time image processing tasks such as edge and line detections, is presented. Resistive grid-based analog structures have been shown to have advantages of compact area, noise immunity, and lower power consumption compared to their digital counterparts. However, these are static structures that can only perform one type of image processing task. The proposed unit cell structure employs 3-D confined resonant tunneling diodes called quantum dots for signal amplification and latching, and these dots are interconnected between neighboring cells through non-volatile continuously variable resistive elements. A method to program connections is introduced and verified through circuit simulations. Various diffusion characteristics, edge detection, and line detection tasks have been demonstrated through simulations using a 2-D array of the proposed cell structure, and analytical models have been provided. In the fourth chapter of this thesis, a bio-inspired hardware designed to solve the optimal control problem for general systems is presented. Adaptive Dynamic Programming algorithms provide means to approximate optimal control actions for linear and non-linear systems. Action-Critic Networks based approach is an efficient way to approximately evaluate the cost function and the optimal control actions. However, due to its computation intensiveness, this approach is usually implemented in high level programming languages run using general purpose processors. The presented hardware design is aimed at reducing the computation time and the hardware overhead by using the Heuristic Dynamic Programming algorithm which is a form of Adaptive Dynamic Programming. The proposed hardware operating at mere speed of 10 MHz yields 237 times faster learning rate in comparison to conventional software implementations running on fast processors such as the 1.2 GHz Intel Xeon processor.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/136972/1/yalciny_1.pd

Designing Neuromorphic Computing Systems with Memristor Devices

Deep Neural Networks (DNNs) have demonstrated fascinating performance in many real-world applications and achieved near human-level accuracy in computer vision, natural video prediction, and many different applications. However, DNNs consume a lot of processing power, especially if realized on General Purpose GPUs or CPUs, which make them unsuitable for low-power applications. On the other hand, neuromorphic computing systems are heavily investigated as a potential substitute for traditional von Neumann systems in high-speed low-power applications. One way to implement neuromorphic systems is to use memristor crossbar arrays because of their small size, low power consumption, synaptic like behavior, and scalability. However, these systems are in their early developing stages and still have many challenges to be solved before commercialization. In this dissertation, we will investigate designing of neuromorphic computing systems, targeting classification and generation applications. Specifically, we introduce three novel neuromorphic computing systems. The first system implements a multi-layer feed-forward neural network, where memristor crossbar arrays are utilized in realizing a novel hybrid spiking-based multi-layered self-learning system. This system is capable of on-chip training, whereas for most previously published systems training is done off-chip. The system performance is evaluated using three different datasets showing improved average failure error by 42% than previously published systems and great immunity against process variations. The second system implements an Echo State Network (ESN), as a special type of recurrent neural networks, by utilizing a novel memristor double crossbar architecture. The system has been trained for sample generation, using the Mackey-Glass dataset, and simulations show accurate sample generation within a 75% window size of the training dataset. Finally, we introduce a novel neuromorphic computing for real-time cardiac arrhythmia classification. Raw ECG data is directly fed to the system, without any feature extraction, and hence reducing classification time and power consumption. The proposed system achieves an overall accuracy of 96.17% and requires only 34 ms to test one ECG beat, which outperforms most of its counterparts. For future work, we introduce a preliminary neuromorphic system implementing a deep Generative Adversarial Network (GAN), based on ESNs. The system is called ESN-GAN and it targets natural video generation applications

ANALOG SIGNAL PROCESSING SOLUTIONS AND DESIGN OF MEMRISTOR-CMOS ANALOG CO-PROCESSOR FOR ACCELERATION OF HIGH-PERFORMANCE COMPUTING APPLICATIONS

Emerging applications in the field of machine vision, deep learning and scientific simulation require high computational speed and are run on platforms that are size, weight and power constrained. With the transistor scaling coming to an end, existing digital hardware architectures will not be able to meet these ever-increasing demands. Analog computation with its rich set of primitives and inherent parallel architecture can be faster, more efficient and compact for some of these applications. The major contribution of this work is to show that analog processing can be a viable solution to this problem. This is demonstrated in the three parts of the dissertation. In the first part of the dissertation, we demonstrate that analog processing can be used to solve the problem of stereo correspondence. Novel modifications to the algorithms are proposed which improves the computational speed and makes them efficiently implementable in analog hardware. The analog domain implementation provides further speedup in computation and has lower power consumption than a digital implementation. In the second part of the dissertation, a prototype of an analog processor was developed using commercially available off-the-shelf components. The focus was on providing experimental results that demonstrate functionality and to show that the performance of the prototype for low-level and mid-level image processing tasks is equivalent to a digital implementation. To demonstrate improvement in speed and power consumption, an integrated circuit design of the analog processor was proposed, and it was shown that such an analog processor would be faster than state-of-the-art digital and other analog processors. In the third part of the dissertation, a memristor-CMOS analog co-processor that can perform floating point vector matrix multiplication (VMM) is proposed. VMM computation underlies some of the major applications. To demonstrate the working of the analog co-processor at a system level, a new tool called PSpice Systems Option is used. It is shown that the analog co-processor has a superior performance when compared to the projected performances of digital and analog processors. Using the new tool, various application simulations for image processing and solution to partial differential equations are performed on the co-processor model