Approches d'optimisation et de personnalisation des réseaux sur puce (NoC : Networks on Chip)

Systems-on-chip (SoC) have become more and more complex due to the development of integrated circuit technology.Recent studies have shown that in order to improve the performance of a specific SoC application domain, the on-chipinter-connects (OCI) architecture must be customized at design-time or at run-time. Related approaches generallyprovide application-specific SoCs tailored to specific applications. The aim of this thesis is to carry out new approachesfor Network-on-Chip (NoC) and study their performances, especially in terms of latency, throughput, energyconsumption and simplicity of implementation.We have proposed an approach to allow designers to customize a candidate OCI architecture by adding strategiclinks in order to match large application workload. The analytical evaluation focuses on improving the physicalparameters of the NoC topology regardless of the application that should run on. The evaluation by simulationfocuses to evaluate the communication performances of the NoC. Simulations results show the effectiveness ofthis approach to improve the NoC performances. We have also introduced a compartmental Fluid-flow basedmodeling approach to allocate required resource for each buffer based on the application traffic pattern. Simulationsare conducted and results show the efficiency of this modeling method for a buffer space optimized allocation.Finally, we proposed a joint approach based on a system dynamics theory for evaluating the performance of a flowcontrol algorithm in NoCs. This algorithm allows NoC elements to dynamically adjust their inflow by using afeedback control-based mechanism. Analytical and simulation results showed the viability of this mechanism forcongestion avoidance in NoCs.Les systèmes embarqués sur puce (SoC : Systems-on-Chip) sont devenus de plus en plus complexes grâce à l’évolution de la technologie des circuits intégrés. Des études récentes ont montré que pour améliorer les performances du réseau su puce (NoC : Network-on-Chip), l’architecture de celui-ci pouvait être personnalisée, soit au moment de la conception, soit au moment de l’exécution. L’objectif principal de cette thèse est d’implémenter de nouvelles approches pour améliorer les performances des NoCs, notamment la latence, le débit, la consommation d’énergie, et la simplicité de mise en œuvre.Nous avons proposé une approche pour permettre aux concepteurs de personnaliser l'architecture d’un NoC par insertion de liens stratégiques, pour qu’elle soit adaptée à de nombreuses applications, sous la contrainte d’un budget limité en termes de nombre de liens. L’évaluation analytique porte sur l’amélioration des paramètres physiques de la topologie du NoC sans tenir compte de l’application qui devrait s’exécuter dessus. L’évaluation par simulation porte sur l’évaluation des performances de communication du NoC. Les résultats de simulations montrent l’efficacité de notre approche pour améliorer les performances du NoC. Nous avons également introduit une approche de modélisation par réseau à compartiments pour allouer les ressources nécessaires pour chaque tampon selon le modèle de trafic de l'application cible. Les résultats de simulations montrent l'efficacité de cette approche de modélisation pour l’allocation optimisée de l'espace tampon. Enfin, nous avons proposé une approche conjointe basée sur la théorie des systèmes dynamiques pour évaluer la performance d'un algorithme de contrôle de flux dans les NoCs. Cet algorithme permet aux éléments du NoC d’ajuster dynamiquement leur entrée en utilisant un mécanisme basé sur le contrôle de flux par rétroaction. Les résultats d’évaluations analytiques et de simulation montrent la viabilité de ce mécanisme pour éviter la congestion dans les NoCs

A Company-led Methodology for the Specification of Product Design Capabilities in Small and Medium Sized Electronics Companies

It is the aim of the research reported in this thesis to improve the product design effectiveness of small and medium sized electronics companies in the United Kingdom. It does so by presenting a methodology for use by such firms which will enable them to specify product design capabilities which are resilient to changes in their respective business environments. The research has not, however, concerned itself with the details of particular electronics component technologies or with the advantages of various CAD or CAE products, although these are both important aspects of any design capability. Nor is it concerned with the implementation of the product design capability. The methodology, which represents a significant improvement on current practice, is a structured, company-driven approach which draws extensively upon the lessons of international design best practice. It uses well-proven tools and techniques to guide firms through the entire process of creating such capabilities - from the development of an appropriate Mission Statement to the identification of cost effective and appropriate design system solutions which can readily be translated into action plans for improvement. The work emphasises the importance of adopting a holistic, systems approach which acknowledges the interrelationship between the management of the design process, as well as its operational and supporting activities. The research has been structured around the experiences of companies which have implemented electronics design systems and which "own" the problem in question. Hence, a research strategy was adopted which was based upon a case study approach and upon the development of close collaborative links with two leading design automation tool vendor companies. Case study interviews were undertaken in 18 U.K. and European electronics companies and in 11 U.S., Japanese and Korean electronics firms. The work proceeded in two distinct phases. Firstly, the author participated with other researchers to jointly develop a functional specification of an electronics designers' toolset to support the process of product design in an integrated manufacturing environment. The first phase provided the context for Phase 2, the development of the AGILITY methodology for specifying product design capabilities which represents the author's individual contribution. The contribution to knowledge made by the research lies in the creation of a process methodology which, for the first time, will help U.K. electronics companies to define for themselves product design capabilities which are robust and which support their wider business objectives. No such methodology is currently available in a form which is both accessible and affordable to smaller firms. Furthermore, the author has uncovered no evidence of the existence of such a methodology even for use by large electronics firms. Validation of the methodology is subject to an ongoing process of feedback.Racal Redac Lt

LIPIcs, Volume 251, ITCS 2023, Complete Volume

LIPIcs, Volume 251, ITCS 2023, Complete Volum