Understanding the Effect of Transpilation in the Reliability of Quantum Circuits

Transpiling is a necessary step to map a logical quantum algorithm to a circuit executed on a physical quantum machine, according to the available gate set and connectivity topology. Different transpiling approaches try to minimize the most critical parameters for the current transmon technology, such as Depth and CNOT number. Crucially, these approaches do not take into account the reliability of the circuit. In particular, transpilation can modify how radiation-induced transient faults propagate. In this paper, we aim at advancing the understanding of transpilation impact on fault propagation by investigating the low-level reliability of several transpiling approaches. We considered 4 quantum algorithms transpiled for 2 different architectures, increasing the number of qubits, and all possible logical-to-physical qubit mapping, adding to a total of 4, 640 transpiled circuits. We inject a total of 202, 124 faults and track their propagation. Our experiments show that by simply choosing the proper transpilation, the reliability of the circuit can improve by up to 14%

Novel Defect Terminolgy Beside Evaluation And Design Fault Tolerant Logic Gates In Quantum-Dot Cellular Automata

Quantum dot Cellular Automata (QCA) is one of the important nano-level technologies for implementation of both combinational and sequential systems. QCA have the potential to achieve low power dissipation and operate high speed at THZ frequencies. However large probability of occurrence fabrication defects in QCA, is a fundamental challenge to use this emerging technology. Because of these various defects, it is necessary to obtain exhaustive recognition about these defects. In this paper a complete survey of different QCA faults are presented first. Then some techniques to improve fault tolerance in QCA circuits explained. The effects of missing cell as an important fault on XOR gate that is one of important basic building block in QCA technology is then discussed by exhaustive simulations. Improvement technique is then applied to these XOR structures and then structures are resimulated to measure their fault tolerance improvement due to using these fault tolerance technique. The result show that different QCA XOR gates have different sensitivity against this fault. After using improvement technique, the tolerance of XOR gates have been increased, furthermore in terms of sensitivity against this defect XORs show similar behavior that indicate the effectiveness of improvement have been made

An assessment of quantum phase estimation protocols for early fault-tolerant quantum computers

We compare several quantum phase estimation (QPE) protocols intended for early fault-tolerant quantum computers (EFTQCs) in the context of models of their implementations on a surface code architecture. We estimate the logical and physical resources required to use these protocols to calculate the ground state energy of molecular hydrogen in a minimal basis with error below $10^{-3}$ atomic units in the presence of depolarizing logical errors. Accounting for the overhead of rotation synthesis and magic state distillation, we find that the total $T$-gate counts do not vary significantly among the EFT QPE protocols at fixed state overlap. In addition to reducing the number of ancilla qubits and circuit depth, the noise robustness of the EFT protocols can be leveraged to reduce resource requirements below those of textbook QPE, realizing approximately a 300-fold reduction in computational volume in some cases. Even so, our estimates are well beyond the scale of existing early fault-tolerance demonstrations.Comment: 14 pages, 15 figure

HARDWARE ATTACK DETECTION AND PREVENTION FOR CHIP SECURITY

Hardware security is a serious emerging concern in chip designs and applications. Due to the globalization of the semiconductor design and fabrication process, integrated circuits (ICs, a.k.a. chips) are becoming increasingly vulnerable to passive and active hardware attacks. Passive attacks on chips result in secret information leaking while active attacks cause IC malfunction and catastrophic system failures. This thesis focuses on detection and prevention methods against active attacks, in particular, hardware Trojan (HT). Existing HT detection methods have limited capability to detect small-scale HTs and are further challenged by the increased process variation. We propose to use differential Cascade Voltage Switch Logic (DCVSL) method to detect small HTs and achieve a success rate of 66% to 98%. This work also presents different fault tolerant methods to handle the active attacks on symmetric-key cipher SIMON, which is a recent lightweight cipher. Simulation results show that our Even Parity Code SIMON consumes less area and power than double modular redundancy SIMON and Reversed-SIMON, but yields a higher fault -detection-failure rate as the number of concurrent faults increases. In addition, the emerging technology, memristor, is explored to protect SIMON from passive attacks. Simulation results indicate that the memristor-based SIMON has a unique power characteristic that adds new challenges on secrete key extraction

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results