Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures

Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits. This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses different CMOS implementations of NCL gates and proposes new circuit techniques to enhance their operation. The second section focuses on mapping multi-rail logic expressions to a standard NCL gate library, which is a form of technology mapping for a category of NCL design automation flows. Finally, the last section proposes design for testability techniques for a recently developed low-power variant of NCL called Sleep Convention Logic (SCL)

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Area-power-delay trade-off in logic synthesis

This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis system. To achieve this, a new delay model is presented, which gives accurate delay estimations for arbitrary sets of Boolean expressions. This allows use of this delay model already during the very first steps of logic synthesis. Furthermore, new algorithms are presented for a number of different optimization tasks within logic synthesis. There are new algorithms to create prime irredundant Boo lean expressions, to perform technology mapping for use with standard cell generators, and to perform gate sizing. To prove the validity of the presented ideas, benchmark results are given throughout the thesis

Hardware optimizations of dense binary hyperdimensional computing: Rematerialization of hypervectors, binarized bundling, and combinational associative memory

Brain-inspired hyperdimensional (HD) computing models neural activity patterns of the very size of the brain's circuits with points of a hyperdimensional space, that is, with hypervectors. Hypervectors are Ddimensional (pseudo)random vectors with independent and identically distributed (i.i.d.) components constituting ultra-wide holographic words: D = 10,000 bits, for instance. At its very core, HD computing manipulates a set of seed hypervectors to build composite hypervectors representing objects of interest. It demands memory optimizations with simple operations for an efficient hardware realization. In this article, we propose hardware techniques for optimizations of HD computing, in a synthesizable open-source VHDL library, to enable co-located implementation of both learning and classification tasks on only a small portion of Xilinx UltraScale FPGAs: (1)We propose simple logical operations to rematerialize the hypervectors on the fly rather than loading them from memory. These operations massively reduce the memory footprint by directly computing the composite hypervectors whose individual seed hypervectors do not need to be stored in memory. (2) Bundling a series of hypervectors over time requires a multibit counter per every hypervector component. We instead propose a binarized back-to-back bundling without requiring any counters. This truly enables onchip learning with minimal resources as every hypervector component remains binary over the course of training to avoid otherwise multibit components. (3) For every classification event, an associative memory is in charge of finding the closest match between a set of learned hypervectors and a query hypervector by using a distance metric. This operator is proportional to hypervector dimension (D), and hence may take O(D) cycles per classification event. Accordingly, we significantly improve the throughput of classification by proposing associative memories that steadily reduce the latency of classification to the extreme of a single cycle. (4) We perform a design space exploration incorporating the proposed techniques on FPGAs for a wearable biosignal processing application as a case study. Our techniques achieve up to 2.39 7 area saving, or 2,337 7 throughput improvement. The Pareto optimal HD architecture is mapped on only 18,340 configurable logic blocks (CLBs) to learn and classify five hand gestures using four electromyography sensors

Multi-level Logic Benchmarks: An Exactness Study

In this paper, we study exact multi-level logic benchmarks. We refer to an exact logic benchmark, or exact benchmark in short, as the optimal implementation of a given Boolean function, in terms of minimum number of logic levels and/or nodes. Exact benchmarks are of paramount importance to design automation because they allow engineers to test the efficiency of heuristic techniques used in practice. When dealing with two-level logic circuits, tools to generate exact benchmarks are available, e.g., espresso-exact, and scale up to relatively large size. However, when moving to modern multi-level logic circuits, the problem of deriving exact benchmarks is inherently more complex. Indeed, few solutions are known. In this paper, we present a scalable method to generate exact multi-level benchmarks with the optimum, or provably close to the optimum, number of logic levels. Our technique involves concepts from graph theory and joint support decomposition. Experimental results show an asymptotic exponential gap between state-of- the-art synthesis techniques and our exact results. Our findings underline the need for strong new research in logic synthesis

Investigation on electricity market designs enabling demand response and wind generation

Demand Response (DR) comprises some reactions taken by the end-use customers to decrease or shift the electricity consumption in response to a change in the price of electricity or a specified incentive payment over time. Wind energy is one of the renewable energies which has been increasingly used throughout the world. The intermittency and volatility of renewable energies, wind energy in particular, pose several challenges to Independent System Operators (ISOs), paving the way to an increasing interest on Demand Response Programs (DRPs) to cope with those challenges. Hence, this thesis addresses various electricity market designs enabling DR and Renewable Energy Systems (RESs) simultaneously. Various types of DRPs are developed in this thesis in a market environment, including Incentive-Based DR Programs (IBDRPs), Time-Based Rate DR Programs (TBRDRPs) and combinational DR programs on wind power integration. The uncertainties of wind power generation are considered through a two-stage Stochastic Programming (SP) model. DRPs are prioritized according to the ISO’s economic, technical, and environmental needs by means of the Technique for Order Preference by Similarity to Ideal Solution (TOPSIS) method. The impacts of DRPs on price elasticity and customer benefit function are addressed, including the sensitivities of both DR parameters and wind power scenarios. Finally, a two-stage stochastic model is applied to solve the problem in a mixed-integer linear programming (MILP) approach. The proposed model is applied to a modified IEEE test system to demonstrate the effect of DR in the reduction of operation cost.A Resposta Dinâmica dos Consumidores (DR) compreende algumas reações tomadas por estes para reduzir ou adiar o consumo de eletricidade, em resposta a uma mudança no preço da eletricidade, ou a um pagamento/incentivo específico. A energia eólica é uma das energias renováveis que tem sido cada vez mais utilizada em todo o mundo. A intermitência e a volatilidade das energias renováveis, em particular da energia eólica, acarretam vários desafios para os Operadores de Sistema (ISOs), abrindo caminho para um interesse crescente nos Programas de Resposta Dinâmica dos Consumidores (DRPs) para lidar com esses desafios. Assim, esta tese aborda os mercados de eletricidade com DR e sistemas de energia renovável (RES) simultaneamente. Vários tipos de DRPs são desenvolvidos nesta tese em ambiente de mercado, incluindo Programas de DR baseados em incentivos (IBDRPs), taxas baseadas no tempo (TBRDRPs) e programas combinados (TBRDRPs) na integração de energia eólica. As incertezas associadas à geração eólica são consideradas através de um modelo de programação estocástica (SP) de dois estágios. Os DRPs são priorizados de acordo com as necessidades económicas, técnicas e ambientais do ISO por meio da técnica para ordem de preferência por similaridade com a solução ideal (TOPSIS). Os impactes dos DRPs na elasticidade do preço e na função de benefício ao cliente são abordados, incluindo as sensibilidades dos parâmetros de DR e dos cenários de potência eólica. Finalmente, um modelo estocástico de dois estágios é aplicado para resolver o problema numa abordagem de programação linear inteira mista (MILP). O modelo proposto é testado num sistema IEEE modificado para demonstrar o efeito da DR na redução do custo de operação