6 research outputs found

    Predicting aging caused delay degradation with alternative IDDT testing in a VLIW processor

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    A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing

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    Unit-based functional IDDT testing for aging degradation monitoring in a VLIW processor

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    In this paper, functional unit-based IDDT testing has been applied for a 90nm VLIW processor to monitor its aging degradation. This technique can provide health data for reliability evaluation as used in e.g. prognostic software for lifetime prediction. The test-program development based on the architecture of a single DSP processor, as well as implementation of an accelerated test (AT) is investigated and IDDT measurement results are evaluated. It is found that decrements of peak IDDT values of crucial functional units inside the processor characterize the power-law degradation with the aging time. This is in coherence with the aging behaviour of (PMOS) transistors caused by Negative-Bias-Temperature-Instability (NBTI), thereby validating the feasibility of this technique in monitoring target-process aging degradation
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