Using Nyquist or Nyquist-Like Plot to Predict Three Typical Instabilities in DC-DC Converters

By transforming an exact stability condition, a new Nyquist-like plot is proposed to predict occurrences of three typical instabilities in DC-DC converters. The three instabilities are saddle-node bifurcation (coexistence of multiple solutions), period-doubling bifurcation (subharmonic oscillation), and Neimark bifurcation (quasi-periodic oscillation). In a single plot, it accurately predicts whether an instability occurs and what type the instability is. The plot is equivalent to the Nyquist plot, and it is a useful design tool to avoid these instabilities. Nine examples are used to illustrate the accuracy of this new plot to predict instabilities in the buck or boost converter with fixed or variable switching frequency.Comment: Submitted to an IEEE journal in 201

Closed-Form Critical Conditions of Subharmonic Oscillations for Buck Converters

A general critical condition of subharmonic oscillation in terms of the loop gain is derived. Many closed-form critical conditions for various control schemes in terms of converter parameters are also derived. Some previously known critical conditions become special cases in the generalized framework. Given an arbitrary control scheme, a systematic procedure is proposed to derive the critical condition for that control scheme. Different control schemes share similar forms of critical conditions. For example, both V2 control and voltage mode control have the same form of critical condition. A peculiar phenomenon in average current mode control where subharmonic oscillation occurs in a window value of pole can be explained by the derived critical condition. A ripple amplitude index to predict subharmonic oscillation proposed in the past research has limited application and is shown invalid for a converter with a large pole.Comment: Submitted to an IEEE Journal on Dec. 23, 2011, and resubmitted to IEEE Transactions on Circuits and Systems-I on Feb. 14, 2012. My current six papers in arXiv have a common reviewe

Bifurcation Boundary Conditions for Switching DC-DC Converters Under Constant On-Time Control

Sampled-data analysis and harmonic balance analysis are applied to analyze switching DC-DC converters under constant on-time control. Design-oriented boundary conditions for the period-doubling bifurcation and the saddle-node bifurcation are derived. The required ramp slope to avoid the bifurcations and the assigned pole locations associated with the ramp are also derived. The derived boundary conditions are more general and accurate than those recently obtained. Those recently obtained boundary conditions become special cases under the general modeling approach presented in this paper. Different analyses give different perspectives on the system dynamics and complement each other. Under the sampled-data analysis, the boundary conditions are expressed in terms of signal slopes and the ramp slope. Under the harmonic balance analysis, the boundary conditions are expressed in terms of signal harmonics. The derived boundary conditions are useful for a designer to design a converter to avoid the occurrence of the period-doubling bifurcation and the saddle-node bifurcation.Comment: Submitted to International Journal of Circuit Theory and Applications on August 10, 2011; Manuscript ID: CTA-11-016

Sampled-Data and Harmonic Balance Analyses of Average Current-Mode Controlled Buck Converter

Dynamics and stability of average current-mode control of buck converters are analyzed by sampled-data and harmonic balance analyses. An exact sampled-data model is derived. A new continuous-time model "lifted" from the sampled-data model is also derived, and has frequency response matched with experimental data reported previously. Orbital stability is studied and it is found unrelated to the ripple size of the current-loop compensator output. An unstable window of the current-loop compensator pole is found by simulations, and it can be accurately predicted by sampled-data and harmonic balance analyses. A new S plot accurately predicting the subharmonic oscillation is proposed. The S plot assists pole assignment and shows the required ramp slope to avoid instability.Comment: Submitted to International Journal of Circuit Theory and Applications on August 9, 2011; Manuscript ID: CTA-11-016

Unified model of voltage/current mode control to predict saddle-node bifurcation

A unified model of voltage mode control (VMC) and current mode control (CMC) is proposed to predict the saddle-node bifurcation (SNB). Exact SNB boundary conditions are derived, and can be further simplified in various forms for design purpose. Many approaches, including steady-state, sampled-data, average, harmonic balance, and loop gain analyses are applied to predict SNB. Each approach has its own merits and complement the other approaches.Comment: Submitted to International Journal of Circuit Theory and Applications on December 23, 2010; Manuscript ID: CTA-10-025

Polynomial Curve Slope Compensation for Peak-Current-Mode-Controlled Power Converters

Linear ramp slope compensation (LRC) and quadratic slope compensation (QSC) are commonly implemented in peak-current-mode-controlled dc-dc converters in order to minimize subharmonic and chaotic oscillations. Both compensating schemes rely on the linearized state-space averaged model (LSSA) of the converter. The LSSA ignores the impact that switching actions have on the stability of converters. In order to include switching events, the nonlinear analysis method based on the Monodromy matrix was introduced to describe a complete-cycle stability. Analyses on analog-controlled dc-dc converters applying this method show that system stability is strongly dependent on the change of the derivative of the slope at the time of switching instant. However, in a mixed-signal-controlled system, the digitalization effect contributes differently to system stability. This paper shows a full complete-cycle stability analysis using this nonlinear analysis method, which is applied to a mixed-signal-controlled converter. Through this analysis, a generalized equation is derived that reveals for the first time the real boundary stability limits for LRC and QSC. Furthermore, this generalized equation allows the design of a new compensating scheme, which is able to increase system stability. The proposed scheme is called polynomial curve slope compensation (PCSC) and it is demonstrated that PCSC increases the stable margin by 30% compared to LRC and 20% to QSC. This outcome is proved experimentally by using an interleaved dc-dc converter that is built for this work

A Modified Boost Converter with Reduced Input Current Ripple

Battery-powered trends in consumer electronics, transportation, and renewable energy sectors increase demands on DC/DC converter technology. Higher switching frequency and efficiency reduces solution size and cost, while increasing power capabilities. Still, switching noise remains the primary drawback associated with any DC/DC converter. Reducing a converter’s input ripple helps prevent switching noise from spreading to other systems on a shared DC power bus. This thesis covers the analysis, simulation, and implementation of a recently-proposed boost converter topology, alongside an equivalent standard boost converter, operating in steady-state, continuous conduction mode. A Matlab-based simulation predicts each converter’s input ripple performance using a state-space model. The converters’ hardware implementation minimizes component and layout differences to create an equivalent comparison. The simulation and hardware measurements demonstrate a 40% input current ripple reduction using the modified topology. Replacing standard boost converters with the modified topology minimizes the switching noise conducted through a system’s DC power network