3D integrated superconducting qubits

As the field of superconducting quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence ($T_1$, $T_{2,\rm{echo}} > 20\,\mu$s) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips

Numerical modelling of a high temperature power module technology with SiC devices for high density power electronics

This paper presents the development of a new packaging technology using silicon carbide (SiC) power devices. These devices will be used in the next power electronic converters. They will provide higher densities, switching frequencies and operating temperature than current Si technologies. Thus the new designed packaging has to take into account such new constraints. The presented work tries to demonstrate the importance of packaging designs for the performance and reliability of integrated SiC power modules. In order to increase the integrated density in power modules, packaging technologies consisting of two stacked substrates with power devices and copper bumps soldered between them were proposed into two configurations. Silver sintering technique is used as die-attach material solution. In order to assess the assembling process and robustness of these packaging designs, the thermo-mechanical behaviour is studied using FEM modelling. Finally, some recommendations are made in order to choose the suitable design for reliable power module

Thermosonic flip chip interconnection using electroplated copper column arrays

Published versio

Study of bonding methods for flip chip and beam leaded devices

The results are presented of a comprehensive study and evaluation for the bonding of flip chip and beam leaded devices onto hybrid microcircuit substrates used in high reliability space applications. The program included the evaluation of aluminum flip chips, solder (silver/tin) bump chips, gold beam leaded devices, and aluminum beam leaded devices

Method to Improve Indium Bump Bonding via Indium Oxide Removal Using a Multi-Step Plasma Process

A process for removing indium oxide from indium bumps in a flip-chip structure to reduce contact resistance, by a multi-step plasma treatment. A first plasma treatment of the indium bumps with an argon, methane and hydrogen plasma reduces indium oxide, and a second plasma treatment with an argon and hydrogen plasma removes residual organics. The multi-step plasma process for removing indium oxide from the indium bumps is more effective in reducing the oxide, and yet does not require the use of halogens, does not change the bump morphology, does not attack the bond pad material or under-bump metallization layers, and creates no new mechanisms for open circuits

Laser-assisted bumping for flip chip assembly

Published versio

Au-SN Flip-Chip Solder Bump for Microelectronic and Optoelectronic Applications

As an alternative to the time-consuming solder pre-forms and pastes currently used, a co-electroplating method of eutectic Au-Sn alloy was used in this study. Using a co-electroplating process, it was possible to plate the Au-Sn solder directly onto a wafer at or near the eutectic composition from a single solution. Two distinct phases, Au5Sn and AuSn, were deposited at a composition of 30at.%Sn. The Au-Sn flip-chip joints were formed at 300 and 400 degrees without using any flux. In the case where the samples were reflowed at 300 degrees, only an (Au,Ni)3Sn2 IMC layer formed at the interface between the Au-Sn solder and Ni UBM. On the other hand, two IMC layers, (Au,Ni)3Sn2 and (Au,Ni)3Sn, were found at the interfaces of the samples reflowed at 400 degrees. As the reflow time increased, the thickness of the (Au,Ni)3Sn2 and (Au,Ni)3Sn IMC layers formed at the interface increased and the eutectic lamellae in the bulk solder coarsened.Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions

Production and Characterisation of SLID Interconnected n-in-p Pixel Modules with 75 Micrometer Thin Silicon Sensors

The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. Targeting at a usage at the high luminosity upgrade of the LHC accelerator called HL-LHC, the results were obtained before and after irradiation up to fluences of $10^{16}$ $\mathrm{n}_{\mathrm{eq}}/\mathrm{cm}^2$ (1 MeV neutrons).Comment: 16 pages, 22 figure