CLIFD: A novel image forgery detection technique using digital signatures

The paper presents a new image forgery detection technique. The proposed technique uses digital signatures; it generates a digital signature for each column and embeds the signature in the least significant bits of each corresponding column's selected pixels. The message digest algorithm 5 (MD5) is used for digital signature generation, and the fourleast-significant-bit substitution mechanism is used to embed the signature in the designated pixels. The embedding of the digital signature in the selected pixel remains completely innocent and undetectable for the human visual system. The proposed forgery detection technique has demonstrated significant results against different types of forgeries introduced to digital images and successfully detected and pointed out the forged columns

Dynamic hashing technique for bandwidth reduction in image transmission

Hash functions are widely used in secure communication systems by generating the message digests for detection of unauthorized changes in the files. Encrypted hashed message or digital signature is used in many applications like authentication to ensure data integrity. It is almost impossible to ensure authentic messages when sending over large bandwidth in highly accessible network especially on insecure channels. Two issues that required to be addressed are the large size of hashed message and high bandwidth. A collaborative approach between encoded hash message and steganography provides a highly secure hidden data. The aim of the research is to propose a new method for producing a dynamic and smaller encoded hash message with reduced bandwidth. The encoded hash message is embedded into an image as a stego-image to avoid additional file and consequently the bandwidth is reduced. The receiver extracts the encoded hash and dynamic hashed message from the received file at the same time. If decoding encrypted hash by public key and hashed message from the original file matches the received file, it is considered as authentic. In enhancing the robustness of the hashed message, we compressed or encoded it or performed both operations before embedding the hashed data into the image. The proposed algorithm had achieved the lowest dynamic size (1 KB) with no fix length of the original file compared to MD5, SHA-1 and SHA-2 hash algorithms. The robustness of hashed message was tested against the substitution, replacement and collision attacks to check whether or not there is any detection of the same message in the output. The results show that the probability of the existence of the same hashed message in the output is closed to 0% compared to the MD5 and SHA algorithms. Amongst the benefits of this proposed algorithm is computational efficiency, and for messages with the sizes less than 1600 bytes, the hashed file reduced the original file up to 8.51%

Proposta de implementação dos algoritmos de hash MD5 e SHA-1 em hardware reconfigurável

This work proposes two Application Specific System Processor (ASSP), one to the MD5 algorithm and other to the SHA-1 algorithm implemented on Field Programmable Gate Array (FPGA) Xilinx Virtex 6 xc6vlx240t-1ff1156. The throughput and the occupied area were analyzed for several implementations on parallel instances of those algorithms. The results showed that the hardware proposed for MD5 achieved a better throughput than those found in published articles and it was possible to implement 320 instances of the algorithm in a single FPGA. For the SHA-1 algorithm the throughput and the area occupied by the internal circuits on the chip were also surprising when compared with other papers. Several applications such as password recovery, password validation, and high volume data integrity checking can be performed efficiently and quickly with an ASSP for MD5 and SHA-1. This work also presents a comparative analysis of the energy consumption associated with execution of the MD5 and SHA-1 algorithms for three different hardware platforms, a microprocessor (µP) of 8 bits and 32 bits and the specific application hardware designed for each algorithm. Results of consumption estimation from the processing time (measured in the laboratory) show that the use of dedicated hardware presents significant gains in energy savings.Este trabalho tem como objetivo propor dois hardwares de aplicação específica (Application Specific System Processor, ASSP), sendo um para o algoritmo MD5 e o outro para o algoritmo SHA-1, ambos implementados em um Field Programmable Gate Array (FPGA) Xilinx Virtex 6 xc6vlx240t-1ff1156. As métricas utilizadas para verificar a eficácia das implementações foram a vazão dos dados (throughput), a área de circuito ocupada, e o consumo de energia. Na qual cada uma foi analisada para várias implementações em instâncias paralelas dos algoritmos. Os resultados mostraram que o hardware proposto para o MD5 alcançou um throughput bem superior aos encontrados em artigos publicados e foi possível implementar 320 instâncias do algoritmo em um único FPGA. Para o algoritmo SHA-1 o throughput e a área ocupada pelos circuitos internos no chip também foram surpreendentes. Várias aplicações como, recuperação de senha (por meio do ataque de força bruta), validação de senha e verificação de integridade de grande volume de dados podem ser executadas de forma eficiente e rápida com um ASSP para o MD5 e para o SHA-1. A métrica do consumo de energia foi avaliada por meio de uma análise comparativa com outras três plataformas de hardware distintas, sendo um micro-processador (µP) de 8 bits, um µP de 32 bits e os hardwares de aplicação específica projetados para cada algoritmo. Os resultados de estimativa de consumo a partir do tempo de processamento (medidos em laboratório) mostram que a utilização dos hardwares dedicados apresentam ganhos significativos de economia de energia