8 research outputs found
Low-Power High-Data-Rate Transmitter Design for Biomedical Application
Ph.DDOCTOR OF PHILOSOPH
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking
Sub-harmonic injection locking is employed to generate
the fast-hopping carriers required in UWB systems for
WiMedia. A very small area 90-nm CMOS prototype synthesizes
the frequencies of band group #6 with a hop time shorter than
4 ns. It occupies 0.074 mm^2 and draws 30 mA from a 1.2 V supply.
Phase noise at 8.71 GHz is -112 dBc/Hz at 1 MHz offset. The
design is supported by a thorough analysis that emphasizes the
tradeoffs in the parameters of the proposed system
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Energy-efficient clock generation for communication and computing systems using injection locking
The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of the ring oscillator, enable a fast startup and conveniently generate multiple time-interleaved phases.
A quasi-linear model of injection-locked ring oscillator (ILRO) is utilized to mathematically formulate the frequency and time domain characteristics of the system, as well as the phase noise shaping and jitter tracking behavior. The settling behavior of ILRO is also exploited and shows a strong dependence on the locking range and the initial phase difference of the injected and the resultant oscillation signals.
A forwarded-clock synchronization based on injection locking is designed for a 10 Gb/s photonic interconnect according to the specific features of optical links. A single clock recovery can be used for all the four channels, resulting in a large amount of power and area saving. The applications of sub-harmonic and super-harmonic injection locking in wireless communications for frequency multiplying and division are also discussed
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Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications
High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator
INJECTION-LOCKING TECHNIQUES FOR MULTI-CHANNEL ENERGY EFFICIENT TRANSMITTER
Ph.DDOCTOR OF PHILOSOPH
Frequency Synthesizers and Oscillator Architectures Based on Multi-Order Harmonic Generation
Frequency synthesizers are essential components for modern wireless and wireline communication systems as they provide the local oscillator signal required to transmit and receive data at very high rates. They are also vital for computing devices and microcontrollers as they generate the clocks required to run all the digital circuitry responsible for the high speed computations. Data rates and clocking speeds are continuously increasing to accommodate for the ever growing demand on data and computational power. This places stringent requirements on the performance metrics of frequency synthesizers. They are required to run at higher speeds, cover a wide range of frequencies, provide a low jitter/phase noise output and consume minimum power and area. In this work, we present new techniques and architectures for implementing high speed frequency synthesizers which fulfill the aforementioned requirements.
We propose a new architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband mm-wave frequencies. A prototype of the proposed system is designed and fabricated in 90nm Complementary Metal Oxide Semiconductor (CMOS) technology. Measurement results demonstrated that a very wide tuning range of 5 to 32 GHz can be achieved, which is costly to implement using conventional techniques. Moreover the power consumption per octave resembles that of state-of-the art reports.
Next, we propose the N-Push cyclic coupled ring oscillator (CCRO) architecture to implement two high performance oscillators: (1) a wideband N-Push/M-Push CCRO operating from 3.16-12.8GHz implemented by two harmonic generation operations using the availability of different phases from the CCRO, and (2) a 13-25GHz millimeter-wave N-Push CCRO with a low phase noise performance of -118dBc/Hz at 10MHz. The proposed oscillators achieve low phase noise with higher FOM than state of the art work.
Finally, we present some improvement techniques applied to the performance of phase locked loops (PLLs). We present an adaptive low pass filtering technique which can reduce the reference spur of integer-N charge-pump based PLLs by around 20dB while maintaining the settling time of the original PLL. Another PLL is presented, which features very low power consumption targeting the Medical Implantable Communication Standard. It operates at 402-405 MHz while consuming 600microW from a 1V supply