Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA

IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications. Not all the devices will require of high performance but will require of low power hungry systems since most of them will be powered with a battery. Conventional CMOS technologies cannot cover these needs even scaling it to very small regimes, which appear other problems. Hence, new technologies are emerging to cover the needs of this devices. One promising technology is the UTBB FDSOI, which achieves good performance with very good energy efficiency. This project characterizes this technology to obtain a set of parameters of interest for analog/RF design. Finally, with the help of a low-power design methodology (gm/Id approach), a design of an ULP ULV LNA is performed to check the suitability of this technology for IoT

Design of a Charge Pump-Based Body Bias Generator for FDSOI Circuits

The technique of Body Bias to control threshold voltage is especially suited for FDSOI technology. Given very low voltage energy sources, it is interesting to compensate the associated loss of speed by applying on-chip generated forward body bias (FBB). There are several challenges involved in the use of this new technology with such low input voltages.Electronics circuits powered at near-threshold voltages (ultra-low voltage designs) are desirable for their low power consumption. However, the performance at such voltage supply is degraded. The application of forward body bias to the circuit can counteract the performance loss. FDSOI is a suitable technology to these techniques, due to its high range of body bias voltages. To generate that body bias voltages, positive and negative, charge pumps circuits are designed to be integrated on the chip. This thesis studies the main challenges on the design of such circuits operating at 300 mV to reach voltages of ± 1 V with power consumption lower than 1 µW and how to model it for layout process. In addition, a control circuit is also designed to provide different intermediate body bias voltage

Design of a Charge Pump-Based Body Bias Generator for FDSOI Circuits

The technique of Body Bias to control threshold voltage is especially suited for FDSOI technology. Given very low voltage energy sources, it is interesting to compensate the associated loss of speed by applying on-chip generated forward body bias (FBB). There are several challenges involved in the use of this new technology with such low input voltages.Electronics circuits powered at near-threshold voltages (ultra-low voltage designs) are desirable for their low power consumption. However, the performance at such voltage supply is degraded. The application of forward body bias to the circuit can counteract the performance loss. FDSOI is a suitable technology to these techniques, due to its high range of body bias voltages. To generate that body bias voltages, positive and negative, charge pumps circuits are designed to be integrated on the chip. This thesis studies the main challenges on the design of such circuits operating at 300 mV to reach voltages of ± 1 V with power consumption lower than 1 µW and how to model it for layout process. In addition, a control circuit is also designed to provide different intermediate body bias voltage