A trace-driven approach for fast and accurate simulation of manycore architectures

International audienceThe evolution of manycore sytems, forecasted to feature hundreds of cores by the end of the decade calls for efficient solutions for design space exploration and debugging. Among the relevant existing solutions the well-known gem5 simu-lator provides a rich architecture description framework. However , these features come at the price of prohibitive simulation time that limits the scope of possible explorations to configurations made of tens of cores. To address this limitation, this paper proposes a novel trace-driven simulation approach for efficient exploration of manycore architectures

CLUSIM: simulador de clusters para aplicaciones de cómputo de altas prestaciones basado en OMNeT++

El Grupo de Ingeniería de Software de la Facultad de Ingeniería de la UNJu tiene entre los objetivos de su proyecto de investigación "Definir la configuración adecuada de tolerancia a fallos para diferentes tipos de aplicaciones HPC, teniendo en cuenta los requerimientos de rendimiento y prestaciones del usuario". En este paper se presenta el simulador CLUSIM basado en OMNeT++ que permite simular de forma parametrizable distintas configuraciones de un cluster para aplicaciones HPC. CLUSIM fue pensado como base de un simulador de sistemas de tolerancia a fallos en HPC. En su versión inicial permite simular aspectos de comunicación para aplicaciones tipo Master/Worker. Para llevar a cabo la validación de CLUSIM se consideraron tanto aspectos prestacionales (tiempo de ejecución) como los archivos de trazas generados por el simulador y por las aplicaciones utilizadas en la experimentación. El proceso de validación permitió concluir que, a pesar de las simplificaciones del modelo de simulación, el comportamiento de CLUSIM con otras configuraciones se mantendría cercano al real.Presentado en el X Workshop Procesamiento Distribuido y Paralelo (WPDP)Red de Universidades con Carreras en Informática (RedUNCI

CLUSIM: simulador de clusters para aplicaciones de cómputo de altas prestaciones basado en OMNeT++

El Grupo de Ingeniería de Software de la Facultad de Ingeniería de la UNJu tiene entre los objetivos de su proyecto de investigación "Definir la configuración adecuada de tolerancia a fallos para diferentes tipos de aplicaciones HPC, teniendo en cuenta los requerimientos de rendimiento y prestaciones del usuario". En este paper se presenta el simulador CLUSIM basado en OMNeT++ que permite simular de forma parametrizable distintas configuraciones de un cluster para aplicaciones HPC. CLUSIM fue pensado como base de un simulador de sistemas de tolerancia a fallos en HPC. En su versión inicial permite simular aspectos de comunicación para aplicaciones tipo Master/Worker. Para llevar a cabo la validación de CLUSIM se consideraron tanto aspectos prestacionales (tiempo de ejecución) como los archivos de trazas generados por el simulador y por las aplicaciones utilizadas en la experimentación. El proceso de validación permitió concluir que, a pesar de las simplificaciones del modelo de simulación, el comportamiento de CLUSIM con otras configuraciones se mantendría cercano al real.Presentado en el X Workshop Procesamiento Distribuido y Paralelo (WPDP)Red de Universidades con Carreras en Informática (RedUNCI

Exploiting memory allocations in clusterized many-core architectures

Power-efficient architectures have become the most important feature required for future embedded systems. Modern designs, like those released on mobile devices, reveal that clusterization is the way to improve energy efficiency. However, such architectures are still limited by the memory subsystem (i.e., memory latency problems). This work investigates an alternative approach that exploits on-chip data locality to a large extent, through distributed shared memory systems that permit efficient reuse of on-chip mapped data in clusterized many-core architectures. First, this work reviews the current literature on memory allocations and explore the limitations of cluster-based many-core architectures. Then, several memory allocations are introduced and benchmarked scalability, performance and energy-wise, compared to the conventional centralized shared memory solution to reveal which memory allocation is the most appropriate for future mobile architectures. Our results show that distributed shared memory allocations bring performance gains and opportunities to reduce energy consumption

Distributed multi-hop reservation scheme for wireless personal area ultra-wideband networks

Ultra-wideband (UWB) technology is a promising technology for multimedia applications in wireless personal area networks (WPANs) that supports very high data rates with lower power transmission for short range communication. The limitation of coverage radius of UWB network necessitates for multihop transmissions. Unfortunately, as the number of hops increases, the quality of service (QoS) degrades rapidly in multihop network. The main goal of this research is to develop and enhance multihop transmission that ensures QoS of real time traffic through the proposed distributed multihop reservation (DMR) scheme. The DMR scheme consists of two modules; distributed multihop reservation protocol (DMRP) and path selection. DMRP incorporates resource reservation, routing and connection setup that are extended on the existing WiMedia Media Access Control protocol (MAC). On the other hand, the path selection determines the optimal path that makes up the multihop route. The path selection selects nodes based on the highest Signal to Interference and Noise Ratio (SINR). The performance of DMR scheme has been verified based on the performance of the video traffic transmission. The main metrics of QoS are measured in terms of Peak Signal- to- Noise ratio (PSNR), End-to-End (E2E) delay, and throughput. The results show that DMRP compared to Multiple Resources Reservation Scheme (MRRS) in six (6) hops transmission has enhanced the average PSNR by 16.5%, reduced the average E2E delay by 14.9% and has increased the throughput by 11.1%. The DMR scheme which is the inclusion of path selection in DMRP has been compared to Link Quality Multihop Relay (LQMR). DMR scheme has improved the video quality transmission by 17.5%, reduced the average E2E delay by 18.6% and enhanced the average throughput by 20.3%. The QoS of six (6) hops transmission employing DMR scheme is almost sustained compared to two hops transmission with the QoS experiencing only slight degradation of about 2.0%. This is a considerable achievement as it is well known that as the number of hops increases the QoS in multihop transmission degrades very rapidly. Thus DMR scheme has shown to significantly improve the performance of real time traffic on UWB multihop network. In general, DMR can be applied to any WPAN network that exploit multihop transmission