Design of a 4GHz programmable frequency synthesizer for IEEE-802.11a standards

Frequency synthesizer is one of the most versatile component and heart of any system. It is used to correct the phase & frequency error so that the signal coming from the different part of the circuit or from the wireless medium does not cause any attenuation or distortion due to frequency dependent or phase dependent error. Present days the Frequency Synthesizer is also used for the wireless communication in the GHz range to correct the phase and frequency error as well as provide synchronization with low locking time, reduced skew and jitter. The frequency synthesizer is used inside a processor to provide the clock synchronization, clock recovery. Due to all above important application in the Analog and mixed signal as well as in digital signal analysis there is a necessity of a Frequency synthesizer with higher Capture range low lock time and with a low settling time. The design of given Frequency synthesizer is done in the 90nm (GPDK 090) process technology in CADANCE virtuoso Analog design environment. To detect the phase and frequency error for any unsymmetrical pulse the voltage based phase frequency detector is used in the design. Voltage controlled oscillator is also a very important part which decide the range of frequency synthesizer. The VCO used here is a current starved Ring oscillator which consumes a very low power. The loop filter is an important component that decides the Dynamic response of the frequency synthesizer. The rise time damping ratio, settling time, bandwidth and output signal to noise ratio of the circuit. The loop filter used here is a passive lead lag filter which is designed with the resistor and capacitor. The layout of the frequency synthesizer is done in the CADANCE virtuoso XL layout editor and different type of simulation is done in the spectre simulator. The power consumed in the frequency synthesizer is 0.22091 m watt at 1.2 V supply voltage and the lock time is 220 ns. The divider is a very important part which made the frequency synthesizer circuit tuneable in a wide range of input frequency so for this purpose we designed it programmable which divide in N/N+1 ratio

Design and Analysis of an Efficient Phase Locked Loop for Fast Phase and Frequency Acquisition

The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high-performance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time. PLL is a mixed signal circuit as its architecture involves both digital and analog signal processing units. The present work focuses on the redesign of a PLL system using the 90 nm process technology (GPDK090 library) in CADENCE Virtuoso Analog Design Environment. Here a current starved ring oscillator has been considered for its superior performance in form of its low chip area, low power consumption and wide tuneable frequency range. The layout structure of the PLL is drawn in CADENCE VirtuosoXL Layout editor. Different types of simulations are carried out in the Spectre simulator. The pre and post layout simulation results of PLL are reported in this work. It is found that the designed PLL consumes 11.68mW power from a 1.8V D.C. supply and have a lock time 280.6 ns. As the voltage controlled oscillator (VCO) is the heart of the PLL, so the optimization of the VCO circuit is also carried out using the convex optimization technique. The results of the VCO designed using the convex optimization method is compared with traditional method