Formal Verification of Full-Wave Rectifier: A Case Study

We present a case study of formal verification of full-wave rectifier for analog and mixed signal designs. We have used the Checkmate tool from CMU [1], which is a public domain formal verification tool for hybrid systems. Due to the restriction imposed by Checkmate it necessitates to make the changes in the Checkmate implementation to implement the complex and non-linear system. Full-wave rectifier has been implemented by using the Checkmate custom blocks and the Simulink blocks from MATLAB from Math works. After establishing the required changes in the Checkmate implementation we are able to efficiently verify the safety properties of the full-wave rectifier.Comment: The IEEE 8th International Conference on ASIC (IEEE ASICON 2009), October 20-23 2009, Changsha, Chin

Statistical Model Checking : An Overview

Quantitative properties of stochastic systems are usually specified in logics that allow one to compare the measure of executions satisfying certain temporal properties with thresholds. The model checking problem for stochastic systems with respect to such logics is typically solved by a numerical approach that iteratively computes (or approximates) the exact measure of paths satisfying relevant subformulas; the algorithms themselves depend on the class of systems being analyzed as well as the logic used for specifying the properties. Another approach to solve the model checking problem is to \emph{simulate} the system for finitely many runs, and use \emph{hypothesis testing} to infer whether the samples provide a \emph{statistical} evidence for the satisfaction or violation of the specification. In this short paper, we survey the statistical approach, and outline its main advantages in terms of efficiency, uniformity, and simplicity.Comment: non

AMS SoC Formal Verification based on Hybrid Scheme

This paper proposes for AMS SoC formal verification based on Hybrid Scheme combined with symbolic computing and LHPN model, FV-HS. The paper is concerned with a class of AMS designs, continuous-time AMS designs i.e., tunnel diode oscillator for research target. Firstly, Labeled Hybrid Petri Net model is established for safety property verification of tunnel diode oscillator, then mathematical expression for this model is extracted for efficiency enhancement, and then proof policy built in computer algebra Maple is applied to the corresponding LHPN model for tunnel diode oscillator to verify the property. The proposed method is implemented on tunnel diode oscillator and experiment results demonstrate the advantages of the proposed method over previous method. The proposed method overcomes the drawbacks of LHPN, makes full use of the merits of LHPN and symbolic computing, simplifies the workflow of algorithm and enhances the efficiency

An optimized method towards formal verification of mixed signals using differential fed neural network over FFNN

Today, the semiconductor industries are rapidly usinganalog and mixed signals to achieve cost-effective solutions on a System on Chip (SoC) design.  The SoC device is a part of analog, digital and essential mixed-signal models/circuits merged on a semiconductor device, which provides the platform to build modern retail/consumer electronics appliances with smart technology. In order to evaluate the mixed signals, the conventional approaches are not effective with respect to its performance, time and manufacturing cost. Thus, the recent researches were much interested in formal verification technique as it provides the evidence of conscious algorithms in a system. The demand for formal verification in the SoC designs in the context of software and hardware platform is high because of its cost and accuracy. Thus, the paper introduces atechnique of formal verification for mixed signals by using training models of the Differential fed neural network (DFNN) over feedforward neural network (FFNN). The formal verification is performed through equivalence checking by using recently adopted designs as reference designs. The outcomes of the verification techniques suggests that DFNN based technique improves the training accuracy and optimizes the hardware resources like area, power than the FFNN based technique

Master of Science

thesisThis document describes an improved method of formal verification of complex analog/mixed-signal (AMS) circuits. Currently, in our LEMA tool, verification properties are encoded using labeled Petri net (LPN). These LPNs are generated manually, a tedious process that requires the user to have considerable familiarity with the tool. To eliminate this time-consuming process, our LEMA tool is extended to include a translator that converts properties written in a property specification language to LPNs. New methods are also implemented to separate the transient period from the stable output period, thus improving the generated model. Also, the current methodology generates the circuit models for the input values used during the simulation of the circuit. So, models generated for other control input values are not accurate. In this case, accuracy of the generated models is improved by using a linear abstraction method like interpolation

Using Stochastic Differential Equation for Verification of Noise in Analog/RF Circuits

Today’s analog/RF design and verification face significant challenges due to circuit complexity, process variations and short market windows. In particular, the influence of technology parameters on circuits, and the issues related to noise modeling and verification still remain a priority for many applications. Noise could be due to unwanted interaction between the circuit elements or it could be inherited from the circuit elements. In addition, manufacturing disparity influence the characteristic behavior of the manufactured circuits. In this paper, we propose a methodology for modeling and verification of analog/RF designs in the presence of noise and process variations. Our approach is based on modeling the designs using stochastic differential equations (SDE) that will allow us to incorporate the statistical nature of noise. We also integrate the device variation due to 0.18μ m fabrication process in an SDE based simulation framework for monitoring properties of interest in order to quickly detect errors. Our approach is illustrated on nonlinear Tunnel-Diode and a Colpitts oscillator circuits

A formal framework for modeling and validating Simulink diagrams

10.1007/s00165-009-0108-9Formal Aspects of Computing215451-483FACM

Integrating Abstraction Techniques for Formal Verification of Analog Designs

The verification of analog designs is a challenging and exhaustive task that requires deep understanding of physical behaviours. In this paper, we propose a qualitative based predicate abstraction method for the verification of a class of non-linear analog circuits. In the proposed method, system equations are automatically extracted from a circuit diagram by means of a bond graph. Verification is applied based on combining techniques from constraint solving and computer algebra along with symbolic model checking. Our methodology has the advantage of avoiding exhaustive simulation normally encountered in the verification of analog designs. To this end, we have used Dymola, Hsolver, SMV and Mathematica to implement the verification flow. We illustrate the methodology on several analog examples including Colpitts and tunnel diode oscillators