Towards a verification technique for large synchronous circuits

Journal ArticleWe present a symbolic simulation based verification approach which can be applied to large synchronous circuits. A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based verification approach efficient. The constraints which are encoded through parametric Boolean expressions can involve the Boolean connectives (-, + , ->), the relational operators (, >, =), and logical connectives (A, V). This technique of using parametric Boolean expressions vastly reduces the number of symbolic simulation vectors and the time for verification, thus making our verification approach applicable to large synchronous circuits. Our verification approach can also be applied for efficient modular verification of large designs; the technique used is to verify each constituent sub-module separately, however in the context of the overall design. Since regular arrays are part of many large designs, we have developed an approach for the verification of regular arrays which combines formal verification at the high level and symbolic simulation at the low level(e.g., switch-level). We show the verification of a circuit called Minmax, a pipelined cache memory system, and an LRU array implementation of the least recently used block replacement policy, to illustrate our verification approach. The experimental results are obtained using the COSMOS symbolic simulator

Towards a verification technique for large synchronous circuits

technical reportWe present a symbolic simulation based veri cation approach which can be applied to large synchronous circuits A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based veri cation approach e cient The constraints which are encoded through parametric Boolean expressions can involve the Boolean con nectives ???? ?? ?? the relational operators ?? ?? ?? ?? ?? ?? and logical connectives ?? This technique of using parametric Boolean expres sions vastly reduces the number of symbolic simulation vectors and the time for veri cation Our veri cation approach can also be applied for e cient modular veri cation of large designs the technique used is to verify each constituent sub module separately?? however in the context of the overall design Since regular arrays are part of many large designs?? we have developed an approach for the veri cation of regular arrays which combines formal veri cation at the high level and symbolic simulation at the low level e g ?? switch level We show the veri cation of a circuit called Minmax?? a pipelined cache memory system?? and an LRU array implementation of the least recently used block replacement policy?? to il lustrate our veri cation approach The experimental results are obtained using the COSMOS symbolic simulato

Optimising Simulation Data Structures for the Xeon Phi

In this paper, we propose a lock-free architecture to accelerate logic gate circuit simulation using SIMD multi-core machines. We evaluate its performance on different test circuits simulated on the Intel Xeon Phi and 2 other machines. Comparisons are presented of this software/hardware combination with reported performances of GPU and other multi-core simulation platforms. Comparisons are also given between the lock free architecture and a leading commercial simulator running on the same Intel hardware

Synchronous Counting and Computational Algorithm Design

Consider a complete communication network on $n$ nodes, each of which is a state machine. In synchronous 2-counting, the nodes receive a common clock pulse and they have to agree on which pulses are "odd" and which are "even". We require that the solution is self-stabilising (reaching the correct operation from any initial state) and it tolerates $f$ Byzantine failures (nodes that send arbitrary misinformation). Prior algorithms are expensive to implement in hardware: they require a source of random bits or a large number of states. This work consists of two parts. In the first part, we use computational techniques (often known as synthesis) to construct very compact deterministic algorithms for the first non-trivial case of $f = 1$. While no algorithm exists for $n < 4$, we show that as few as 3 states per node are sufficient for all values $n \ge 4$. Moreover, the problem cannot be solved with only 2 states per node for $n = 4$, but there is a 2-state solution for all values $n \ge 6$. In the second part, we develop and compare two different approaches for synthesising synchronous counting algorithms. Both approaches are based on casting the synthesis problem as a propositional satisfiability (SAT) problem and employing modern SAT-solvers. The difference lies in how to solve the SAT problem: either in a direct fashion, or incrementally within a counter-example guided abstraction refinement loop. Empirical results suggest that the former technique is more efficient if we want to synthesise time-optimal algorithms, while the latter technique discovers non-optimal algorithms more quickly.Comment: 35 pages, extended and revised versio