Memristor-based design solutions for mitigating parametric variations in IoT applications

PhD ThesisRapid advancement of the internet of things (IoT) is predicated by two important factors of the electronic technology, namely device size and energy-efficiency. With smaller size comes the problem of process, voltage and temperature (PVT) variations of delays which are the key operational parameters of devices. Parametric variability is also an obstacle on the way to allowing devices to work in systems with unpredictable power sources, such as those powered by energy-harvesters. Designers tackle these problems holistically by developing new techniques such as asynchronous logic, where mechanisms such as matching delays are widely used to adapt to delay variations. To mitigate energy efficiency and power interruption issues the matching delays need to be ideally retained in a non-volatile storage. Meanwhile, a resistive memory called memristor becomes a promising component for power-restricted applications owing to its inherent non-volatility. While providing non-volatility, the use of memristor in delay matching incurs some power overheads. This creates the first challenge on the way of introducing memristors into IoT devices for the delay matching. Another important factor affecting the use of memristors in IoT devices is the dependence of the memristor value on temperature. For example, a memristance decoder used in the memristor-based components must be able to correct the read data without incurring significant overheads on the overall system. This creates the second challenge for overcoming the temperature effect in memristance decoding process. In this research, we propose methods for improving PVT tolerance and energy characteristics of IoT devices from the perspective of above two main challenges: (i) utilising memristor to enhance the energy efficiency of the delay element (DE), and (ii) improving the temperature awareness and energy robustness of the memristance decoder. For memristor-based delay element (MemDE), we applied a memristor between two inverters to vary the path resistance, which determines the RC delay. This allows power saving due to the low number of switching components and the absence of external delay storage. We also investigate a solution for avoiding the unintended tuning (UT) and a timing model to estimate the proper pulse width for memristance tuning. The simulation results based on UMC 180nm technology and VTEAM model show the MemDE can provide the delay between 0.55ns and 1.44ns which is compatible to the 4-bit multiplexerbased delay element (MuxDE) in the same technology while consuming thirteen times less power. The key contribution within (i) is the development of low-power MemDE to mitigate the timing mismatch caused by PVT variations. To estimate the temperature effect on memristance, we develop an empirical temperature model which fits both titanium dioxide and silver chalcogenide memristors. The temperature experiments are conducted using the latter device, and the results confirm the validity of the proposed model with the accuracy R-squared >88%. The memristance decoder is designed to deliver two key advantages. Firstly, the temperature model is integrated into the VTEAM model to enable the temperature compensation. Secondly, it supports resolution scalability to match the energy budget. The simulation results of the 2-bit decoder based on UMC 65nm technology show the energy can be varied between 49fJ and 98fJ. This is the second major contribution to address the challenge (ii). This thesis gives future research directions into an in-depth study of the memristive electronics as a variation-robust energy-efficient design paradigm and its impact on developing future IoT applications.sponsored by the Royal Thai Governmen

Development of phase change memory cell electrical circuit model for non-volatile multistate memory device

Phase change memory (PCM) is an emerging non-volatile memory technology that demonstrates promising performance characteristics. The presented research aims to study the feasibility of using resistive non-volatile PCM in embedded memory applications, and in bridging the performance gap in traditional memory hierarchy between volatile and non-volatile memories. The research studies the operation dynamics of PCM, including its electrical, thermal and physical properties; in order to determine its behaviour. A PCM cell circuit model is designed and simulated with the aid of SPICE tools (LTSPICE IV). The first step in the modelling process was to design a single-level PCM (SLPCM) cell circuit model that stores a single bit of data. To design the PCM circuit model; crystallization theory and heat transfer equation were utilized. The developed electrical circuit model evaluates the physical transformations that a PCM cell undergoes in response to an input pulse. Furthermore, the developed model accurately simulated the temperature profile, the crystalline fraction, and the resistance of the cell as a function of the programming pulse. The circuit model is then upgraded into a multilevel phase change memory (MLPCM) cell circuit model. The upgraded MLPCM circuit model stores two bits of data, and incorporates resistance drift with time. The multiple resistance levels were achieved by controlling the programming pulse width in the range of 10ns to 200ns. Additionally, the drift behaviour was precisely evaluated; by using statistical data of drift exponents, and evaluating the exact drift duration. Moreover, the simulation results for the designed SLPCM and MLPCM cell models were found to be in close agreement with experimental data. The simulated I-V characteristics for both SLPCM and MLPCM mimicked the experimentally produced I-V curves. Furthermore, the simulated drift resistance levels matched the experimental data for drift durations up to 103 seconds; which is the available experimental data duration in technical literature. Furthermore, the simulation results of MLPCM showed that the deviation between the programmed and drifted resistance can reach 6x106Ω in less than 1010 seconds. This resistance deviation leads to reading failures in less than 100 seconds after programming, if standard fixed sensing thresholds method was used. Therefore, to overcome drift reliability issues, and retain the density advantage offered by multilevel operation; a time-aware sensing scheme is developed. The designed sensing scheme compensates for the drift caused resistance deviation; by using statistical data of drift coefficients to forecast adaptive sensing thresholds. The simulation results showed that the use of adaptive time-aware sensing thresholds completely eliminated drift reliability issues and read errors. Furthermore, PCM based nanocrossbar memory structure performance in terms of delay and energy consumption is studied in simulation environment. The nanocrossbar is constructed with a grid of connecting wires; and the designed PCM cell circuit model is used as memory element and placed at junction points of the grid. Then the effect of connecting nanowires resistance in PCM nanocrossbar performance is studied in passive crossbars. The resistance of a connecting wire segment was evaluated with physical formulas that calculate nanoscaled conductors’ resistance. Then a resistor that is equivalent to each wire segment resistance is placed in the tested crossbar structure. Simulation results showed that due to connecting wires resistance; the PCM cells are not truly biased to programming voltage and ground. This leads to 40% deviation in the programed low resistive state from the targeted levels. Thus, affecting PCM reliability and decreasing the high to low resistance ratio by 90%. Therefore, programming and architectural solutions to wire resistance related reliability issue ar presented. Where dissipated power across wire resistance is compensated for; by controlling programming pulse duration. The programming solution retained reliability however; it increased programming energy consumption and delay by an average of 40pJ and 60ns respectively per operation. Additionally, the effects of leakage energy in PCM based nanocrossbars were studied in simulation environment. Then, a structural solution was developed and designed. In the designed structure; leakage sneak paths are eliminated by introducing individual word lines to each memory element. This method led to 30% reduction in reading delay, and consumed only about sixth the leakage energy consumed by the standard structure. Moreover, a sensing scheme that aims to reduce energy consumption in PCM based nanocrossbars during reading process was explored. The sensing method is developed using AC current in contrast to the standard DC current reading circuits. In the designed sensing circuit, a low pass filter is utilized. Accordingly, the filter attenuation of the applied AC reading signal indicates the stored state. The proposed circuit design of the AC sensing scheme was constructed and studied in simulation environment. Simulation results showed that AC sensing has reduced reading energy consumption by over 50%; compared to standard DC sensing scheme. Furthermore, the use of SLPCM and MLPCM in memory applications as crossbar memory elements, and in logic applications i.e. PCM based LUTs was explored and tested in simulation environment. The PCM performance in crossbar memory was then compared to current Static Random Access Memory (SRAM) technology and against one of the main emerging resistive non-volatile memory technologies i.e. Memristors. Simulation results showed that programming and reading energy consumption of PCM based crossbars were five orders of magnitude more than SRAM based crossbars. And reading delay of SRAM based crossbars was only 38% of reading delay of PCM based counterparts. However, PCM cells occupies less than 60% of the area required by SRAM and can store multiple bit in a single cell. Moreover, Memristor based nanocrossbars outperformed PCM based ones; in terms of delay and energy consumption. With PCM consuming 2 orders of magnitude more energy during programming and reading. PCM also required 10 times the programming delay. However, PCM crossbars offered higher switching resistance range i.e. 170kΩ compared to the 20kΩ offered by memristors; which support PCM multibit storage capability and higher density

Development of phase change memory cell electrical circuit model for non-volatile multistate memory device

Phase change memory (PCM) is an emerging non-volatile memory technology that demonstrates promising performance characteristics. The presented research aims to study the feasibility of using resistive non-volatile PCM in embedded memory applications, and in bridging the performance gap in traditional memory hierarchy between volatile and non-volatile memories. The research studies the operation dynamics of PCM, including its electrical, thermal and physical properties; in order to determine its behaviour. A PCM cell circuit model is designed and simulated with the aid of SPICE tools (LTSPICE IV). The first step in the modelling process was to design a single-level PCM (SLPCM) cell circuit model that stores a single bit of data. To design the PCM circuit model; crystallization theory and heat transfer equation were utilized. The developed electrical circuit model evaluates the physical transformations that a PCM cell undergoes in response to an input pulse. Furthermore, the developed model accurately simulated the temperature profile, the crystalline fraction, and the resistance of the cell as a function of the programming pulse. The circuit model is then upgraded into a multilevel phase change memory (MLPCM) cell circuit model. The upgraded MLPCM circuit model stores two bits of data, and incorporates resistance drift with time. The multiple resistance levels were achieved by controlling the programming pulse width in the range of 10ns to 200ns. Additionally, the drift behaviour was precisely evaluated; by using statistical data of drift exponents, and evaluating the exact drift duration. Moreover, the simulation results for the designed SLPCM and MLPCM cell models were found to be in close agreement with experimental data. The simulated I-V characteristics for both SLPCM and MLPCM mimicked the experimentally produced I-V curves. Furthermore, the simulated drift resistance levels matched the experimental data for drift durations up to 103 seconds; which is the available experimental data duration in technical literature. Furthermore, the simulation results of MLPCM showed that the deviation between the programmed and drifted resistance can reach 6x106Ω in less than 1010 seconds. This resistance deviation leads to reading failures in less than 100 seconds after programming, if standard fixed sensing thresholds method was used. Therefore, to overcome drift reliability issues, and retain the density advantage offered by multilevel operation; a time-aware sensing scheme is developed. The designed sensing scheme compensates for the drift caused resistance deviation; by using statistical data of drift coefficients to forecast adaptive sensing thresholds. The simulation results showed that the use of adaptive time-aware sensing thresholds completely eliminated drift reliability issues and read errors. Furthermore, PCM based nanocrossbar memory structure performance in terms of delay and energy consumption is studied in simulation environment. The nanocrossbar is constructed with a grid of connecting wires; and the designed PCM cell circuit model is used as memory element and placed at junction points of the grid. Then the effect of connecting nanowires resistance in PCM nanocrossbar performance is studied in passive crossbars. The resistance of a connecting wire segment was evaluated with physical formulas that calculate nanoscaled conductors’ resistance. Then a resistor that is equivalent to each wire segment resistance is placed in the tested crossbar structure. Simulation results showed that due to connecting wires resistance; the PCM cells are not truly biased to programming voltage and ground. This leads to 40% deviation in the programed low resistive state from the targeted levels. Thus, affecting PCM reliability and decreasing the high to low resistance ratio by 90%. Therefore, programming and architectural solutions to wire resistance related reliability issue ar presented. Where dissipated power across wire resistance is compensated for; by controlling programming pulse duration. The programming solution retained reliability however; it increased programming energy consumption and delay by an average of 40pJ and 60ns respectively per operation. Additionally, the effects of leakage energy in PCM based nanocrossbars were studied in simulation environment. Then, a structural solution was developed and designed. In the designed structure; leakage sneak paths are eliminated by introducing individual word lines to each memory element. This method led to 30% reduction in reading delay, and consumed only about sixth the leakage energy consumed by the standard structure. Moreover, a sensing scheme that aims to reduce energy consumption in PCM based nanocrossbars during reading process was explored. The sensing method is developed using AC current in contrast to the standard DC current reading circuits. In the designed sensing circuit, a low pass filter is utilized. Accordingly, the filter attenuation of the applied AC reading signal indicates the stored state. The proposed circuit design of the AC sensing scheme was constructed and studied in simulation environment. Simulation results showed that AC sensing has reduced reading energy consumption by over 50%; compared to standard DC sensing scheme. Furthermore, the use of SLPCM and MLPCM in memory applications as crossbar memory elements, and in logic applications i.e. PCM based LUTs was explored and tested in simulation environment. The PCM performance in crossbar memory was then compared to current Static Random Access Memory (SRAM) technology and against one of the main emerging resistive non-volatile memory technologies i.e. Memristors. Simulation results showed that programming and reading energy consumption of PCM based crossbars were five orders of magnitude more than SRAM based crossbars. And reading delay of SRAM based crossbars was only 38% of reading delay of PCM based counterparts. However, PCM cells occupies less than 60% of the area required by SRAM and can store multiple bit in a single cell. Moreover, Memristor based nanocrossbars outperformed PCM based ones; in terms of delay and energy consumption. With PCM consuming 2 orders of magnitude more energy during programming and reading. PCM also required 10 times the programming delay. However, PCM crossbars offered higher switching resistance range i.e. 170kΩ compared to the 20kΩ offered by memristors; which support PCM multibit storage capability and higher density