First order devices, hybrid memristors, and the frontiers of nonlinear circuit theory

Several devices exhibiting memory effects have shown up in nonlinear circuit theory in recent years. Among others, these circuit elements include Chua's memristors, as well as memcapacitors and meminductors. These and other related devices seem to be beyond the, say, classical scope of circuit theory, which is formulated in terms of resistors, capacitors, inductors, and voltage and current sources. We explore in this paper the potential extent of nonlinear circuit theory by classifying such mem-devices in terms of the variables involved in their constitutive relations and the notions of the differential- and the state-order of a device. Within this framework, the frontier of first order circuit theory is defined by so-called hybrid memristors, which are proposed here to accommodate a characteristic relating all four fundamental circuit variables. Devices with differential order two and mem-systems are discussed in less detail. We allow for fully nonlinear characteristics in all circuit elements, arriving at a rather exhaustive taxonomy of C^1-devices. Additionally, we extend the notion of a topologically degenerate configuration to circuits with memcapacitors, meminductors and all types of memristors, and characterize the differential-algebraic index of nodal models of such circuits.Comment: Published in 2013. Journal reference included as a footnote in the first pag

Asymptotic behavior of memristive circuits

The interest in memristors has risen due to their possible application both as memory units and as computational devices in combination with CMOS. This is in part due to their nonlinear dynamics, and a strong dependence on the circuit topology. We provide evidence that also purely memristive circuits can be employed for computational purposes. In the present paper we show that a polynomial Lyapunov function in the memory parameters exists for the case of DC controlled memristors. Such Lyapunov function can be asymptotically approximated with binary variables, and mapped to quadratic combinatorial optimization problems. This also shows a direct parallel between memristive circuits and the Hopfield-Little model. In the case of Erdos-Renyi random circuits, we show numerically that the distribution of the matrix elements of the projectors can be roughly approximated with a Gaussian distribution, and that it scales with the inverse square root of the number of elements. This provides an approximated but direct connection with the physics of disordered system and, in particular, of mean field spin glasses. Using this and the fact that the interaction is controlled by a projector operator on the loop space of the circuit. We estimate the number of stationary points of the approximate Lyapunov function and provide a scaling formula as an upper bound in terms of the circuit topology only.Comment: 20 pages, 8 figures; proofs corrected, figures changed; results substantially unchanged; to appear in Entrop

Versatile stochastic dot product circuits based on nonvolatile memories for high performance neurocomputing and neurooptimization.

The key operation in stochastic neural networks, which have become the state-of-the-art approach for solving problems in machine learning, information theory, and statistics, is a stochastic dot-product. While there have been many demonstrations of dot-product circuits and, separately, of stochastic neurons, the efficient hardware implementation combining both functionalities is still missing. Here we report compact, fast, energy-efficient, and scalable stochastic dot-product circuits based on either passively integrated metal-oxide memristors or embedded floating-gate memories. The circuit's high performance is due to mixed-signal implementation, while the efficient stochastic operation is achieved by utilizing circuit's noise, intrinsic and/or extrinsic to the memory cell array. The dynamic scaling of weights, enabled by analog memory devices, allows for efficient realization of different annealing approaches to improve functionality. The proposed approach is experimentally verified for two representative applications, namely by implementing neural network for solving a four-node graph-partitioning problem, and a Boltzmann machine with 10-input and 8-hidden neurons

Saddle-Node bifurcations in classical and memristive circuits

This paper addresses a systematic characterization of saddle-node bifurcations in nonlinear electrical and electronic circuits. Our approach is a circuit-theoretic one, meaning that the bifurcation is analyzed in terms of the devices’ characteristics and the graph-theoretic properties of the digraph underlying the circuit. The analysis is based on a reformulation of independent interest of the saddle-node theorem of Sotomayor for semiexplicit index one differential-algebraic equations (DAEs), which define the natural context to set up nonlinear circuit models. The bifurcation is addressed not only for classical circuits, but also for circuits with memristors. The presence of this device systematically leads to nonisolated equilibria, and in this context the saddle-node bifurcation is shown to yield a bifurcation of manifolds of equilibria; in cases with a single memristor, this phenomenon describes the splitting of a line of equilibria into two, with different stability properties