Design methodology and productivity improvement in high speed VLSI circuits

2017 Spring.Includes bibliographical references.To view the abstract, please see the full text of the document

The Design of a System Architecture for Mobile Multimedia Computers

This chapter discusses the system architecture of a portable computer, called Mobile Digital Companion, which provides support for handling multimedia applications energy efficiently. Because battery life is limited and battery weight is an important factor for the size and the weight of the Mobile Digital Companion, energy management plays a crucial role in the architecture. As the Companion must remain usable in a variety of environments, it has to be flexible and adaptable to various operating conditions. The Mobile Digital Companion has an unconventional architecture that saves energy by using system decomposition at different levels of the architecture and exploits locality of reference with dedicated, optimised modules. The approach is based on dedicated functionality and the extensive use of energy reduction techniques at all levels of system design. The system has an architecture with a general-purpose processor accompanied by a set of heterogeneous autonomous programmable modules, each providing an energy efficient implementation of dedicated tasks. A reconfigurable internal communication network switch exploits locality of reference and eliminates wasteful data copies

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

A Structured Design Methodology for High Performance VLSI Arrays

abstract: The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes making the complete design custom schematic but using the standard cells. This requires adding some custom cells to the already exhaustive library to optimize the design for performance. Once schematic is finalized, the designer places these standard cells in a spreadsheet, placing closely the cells in the critical paths. A Perl script then generates Cadence Encounter compatible placement file. The design is then routed in Encounter. Since designer is the best judge of the circuit architecture, placement by the designer will allow achieve most optimal design. Several designs like IPCAM, issue logic, TLB, RF and Cache designs were carried out and the performance were compared against the fully custom and ASIC flow. The TLB, RF and Cache were the part of the HEMES microprocessor.Dissertation/ThesisPh.D. Electrical Engineering 201

A haptically enabled CAN-based steering wheel controller

As the portable entertainment and mobility technologies migrate into the car, driver distraction has become recognized as a major factor in road crashes around the world. To help alert drivers to their distraction, active safety technologies such as lane departure warning systems and collision avoidance systems are being implemented. One issue with the implementation of yet another technology into the vehicle is how to cut through the competing demands of the mobile phone, navigation systems and other technologies. Haptic alerts present just such a method that may enable the system to short-circuit the normal auditory or visual communication channels. This paper presents a low cost haptic steering wheel controller that has been designed developed and tested and may be used as a communication device by a lane departure, collision avoidance, or other type of safety system

Development of the Robotic Touch foot Sensor for 2D walking Robot, for Studying Rough Terrain Locomotion

Many researchers have been developing biped walking robots with excellent techniques and advanced technologies. However, ordinary locomotion is executed on even terrain such as flat surface. This means that many researches are focusing much on image processing, programing techniques and newly suggested devices, but not much research is being done on the proper sensors to robotic feet. Regarding robot gaits on unknown ground, one of the most significant determinations is to investigate balance by itself. A new sensor was studied for the robotic foot in order to allow walking on rough ground by sensing variations in the pressure profile on the foot. The primary purpose of this study is to provide a proper foot sensor for Jaywalker. The Jaywalker has been developed by the Intelligent Systems and Automation Laboratory. Jaywalker provides a good platform for the study of rough terrain walking. The sensor to be developed for the robot must be applicable to every structure and flexible and able to impulsive forces, as well as having a reasonable manufacturing cost.The main concept of this new type of sensor is to utilize the special application and design of inductive touch sensors. The Propeller microprocessor plays an important role in the control of the new sensor. The results of this study indicate that the new inductive sensor can be useful as a robotic foot sensor for the study of rough terrain walking