Novel Design for Dual Edge Triggered Flip-Flop for High Speed Low Power Application

In area of low power VLSI, switching activity of circuit node is of great concerned to reduce dynamic power. Dynamic power is directly proportional to switching activity of nodes. Switching activity vary according to input data pattern thereby for different input data sequence different power dissipation can occur. To achieve same data throughput as in single edged triggered flip-flop (SETFF), dual edged triggered flip-flop (DETFF) is an effective way to decrease power dissipation. DETFF reduces switching activity for same data throughput. In this paper, two different design of DETFF are investigated. The technique used to design DETFF is to generate pulse at every edge of clock to trigger data and/or latch stage of circuit. A conventional and a proposed design of DETFF are surveyed. Proposed DETFF utilized different scheme to generate pulse at every edge of clock. In view of power dissipation there is no considerable improvement but delay has been greatly reduced thereby overall PDP with respect to conventional DETF

Low power VLSI design of a fir filter using dual edge triggered clocking strategy

Digital signal processing is an area of science and engineering that has developed rapidly over the past 30 years. This rapid development is a result of the significant advances in digital computer technology and integrated–circuit fabrication. DSP processors are a diverse group, most share some common features designed to support fast execution of the repetitive, numerically intensive computations characteristic of digital signal processing algorithms. The most often cited of these features is the ability to perform a multiply-accumulate operation (often called a "MAC") in a single instruction cycle. Hence in this project a DSP Processor is designed which can perform the basic DSP Operations like convolution, fourier transform and filtering. The processor designed is a simple 4-bit processor which has single data line of 8-bits and a single address bus of 16-bits. With a set of branch instructions the project DSP will operate as a CISC processor with strong math capabilities and can perform the above mentioned DSP operations. The application I have taken is the low power FIR filter using dual edge clocking strategy. It combines two novel techniques for the power reduction which is : multi stage clock gating and a symmetric two-phase level-sensitive clocking with glitch aware re-distribution of data-path registers. Simulation results confirm a 42% reduction in power over single edge triggered clocking with clock gating.Also to further reduce the power consumption the a low power latch circuit is used. Thanks to a partial pass-transistor logic, it trades time for energy, being particularly suitable for low power low-frequency applications. Simulation results confirm the power reduction. This technique discussed can be implemented to portable devices which needs longer battery life and to ASIC’

Reporte de formación complementaria en área de diseño de circuitos integrados digitales

Reporte de formación complementaria para el área de Diseño de Circuitos Integrados Digitales. Se describen los proyectos realizados para los cursos de Diseño de Sistemas Digitales, Diseño de Circuitos Integrados Digitales y Verificación de Sistemas Digitales. El proyecto para la materia de Diseño de Sistemas Digitales consistió en diseñar un sistema digital que involucre un procesador MIPS32 básico con comunicación con controladores de interface RS-232 y de LCD para la tarjeta de prototipos Spartan-3E SK, con el objetivo de recibir un dato serial de la PC y procesarlo para ser desplegado en una pantalla LCD. El proyecto para Diseño de Circuitos Integrados Digitales consistió en la optimización de los tiempos de “setup” y “hold” de un flip flop tipo D Maestro-Esclavo, con el objetivo de demostrar su impacto en velocidad, área y consumo de potencia. También se diseñó un contador anillo módulo 8 utilizando este flip flop, del cual se analizó su desempeño. El proyecto realizado para el curso de Verificación de Sistemas Digitales consistió en implementar un plan y ambiente de verificación para la unidad despachadora de un Microprocesador de 32 bits implementada a nivel RTL. System Verilog fue usado como lenguaje de verificación

Power Reduction Techniques in Clock Distribution Networks with Emphasis on LC Resonant Clocking

In this thesis we propose a set of independent techniques in the overall concept of LC resonant clocking where each technique reduces power consumption and improve system performance. Low-power design is becoming a crucial design objective due to the growing demand on portable applications and the increasing difficulties in cooling and heat removal. The clock distribution network delivers the clock signal which acts as a reference to all sequential elements in the synchronous system. The clock distribution network consumes a considerable amount of power in synchronous digital systems. Resonant clocking is an emerging promising technique to reduce the power of the clock network. The inductor used in resonant clocking enables the conversion of the electric energy stored on the clock capacitance to magnetic energy in the inductor and vice versa. In this thesis, the concept of the slack in the clock skew has been extended for an LC fully-resonant clock distribution network. This extra slack in comparison to standard clock distribution networks can be used to reduce routing complexity, achieve reduction in wire elongation, total wire length, and power consumption. Simulation results illustrate that by utilizing the proposed approach, an average reduction of 53% in the number of wire elongations and 11% reduction in total wire length can be achieved. A dual-edge clocking scheme introduced in the literature to enable the operation of the flip-flop at the rising- and falling edges of the clock has been modified. The interval by which the charging elements in the flip-flop are being switched-on was reduced causing a reduction in power consumption. Simulating the flip-flop in STMicroelectronics 90-nm technology shows correct functionality of the Sense Amplifier flip-flop with a resonant clock signal of 500 MHz and a throughput of 1 GHz under process, voltage, and temperature (PVT) variations. Modeling the resonant system with the proposed flip-flop illustrates that dual-edge compared to single-edge triggering can achieve up to 58% reduction in power consumption when the clock capacitance is the dominating factor. The application of low-swing clocking to LC resonant clock distribution network has been investigated on-chip. The proposed low-swing resonant clocking scheme operates with one voltage supply and does not require an additional supply voltage. The Differential Conditional Capturing flip-flop introduced in the literature was modified to operate with a low-swing sinusoidal clock. Low-swing resonant clocking achieved around 5.8% reduction in total power with 5.7% area overhead. Modeling the clock network with the proposed flip-flop illustrates that low-swing clocking can achieve up to 58% reduction in the power consumption of the resonant clock. An analytical approach was introduced to estimate the required driver strength in the clock generator. Using the proposed approach early in the design stage reduces area and power overhead by eliminating the need for programmable switches in the driving circuit