3,500 research outputs found
Recommended from our members
Design of a 3 GHz fine resolution LC DCO
In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning. Both delta-sigma modulator and capacitive divider circuit are implemented to achieve a finer resolution and a larger dynamic range. The LC-oscillator has a coarse tuning range from 3.05 GHz to 3.85 GHz and a fine tuning range of 50MHz. It features a phase noise level of -115dBc/Hz at 1MHz frequency offset and consumes 5.4mW. Efficient simulation methodology is explored. Finally, this DCO is simulated in an All-Digital Phase Locked Loop (ADPLL) with other ideal behavior blocks implemented using Verilog-A, and the performance of the DCO is evaluated.Electrical and Computer Engineerin
All-Digital Self-interference Cancellation Technique for Full-duplex Systems
Full-duplex systems are expected to double the spectral efficiency compared
to conventional half-duplex systems if the self-interference signal can be
significantly mitigated. Digital cancellation is one of the lowest complexity
self-interference cancellation techniques in full-duplex systems. However, its
mitigation capability is very limited, mainly due to transmitter and receiver
circuit's impairments. In this paper, we propose a novel digital
self-interference cancellation technique for full-duplex systems. The proposed
technique is shown to significantly mitigate the self-interference signal as
well as the associated transmitter and receiver impairments. In the proposed
technique, an auxiliary receiver chain is used to obtain a digital-domain copy
of the transmitted Radio Frequency (RF) self-interference signal. The
self-interference copy is then used in the digital-domain to cancel out both
the self-interference signal and the associated impairments. Furthermore, to
alleviate the receiver phase noise effect, a common oscillator is shared
between the auxiliary and ordinary receiver chains. A thorough analytical and
numerical analysis for the effect of the transmitter and receiver impairments
on the cancellation capability of the proposed technique is presented. Finally,
the overall performance is numerically investigated showing that using the
proposed technique, the self-interference signal could be mitigated to ~3dB
higher than the receiver noise floor, which results in up to 76% rate
improvement compared to conventional half-duplex systems at 20dBm transmit
power values.Comment: Submitted to IEEE Transactions on Wireless Communication
Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops
This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissipation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed
Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies
CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections
Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs
This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage
Adaptive Multi-Rate Wavelet Method for Circuit Simulation
In this paper a new adaptive algorithm for multi-rate circuit simulation encountered in the design of RF circuits based on spline wavelets is presented. The ordinary circuit differential equations are first rewritten by a system of (multi-rate) partial differential equations (MPDEs) in order to decouple the different time scales. Second, a semi-discretization by Rothe's method of the MPDEs results in a system of differential algebraic equations DAEs with periodic boundary conditions. These boundary value problems are solved by a Galerkin discretization using spline functions. An adaptive spline grid is generated, using spline wavelets for non-uniform grids. Moreover the instantaneous frequency is chosen adaptively to guarantee a smooth envelope resulting in large time steps and therefore high run time efficiency. Numerical tests on circuits exhibiting multi-rate behavior including mixers and PLL conclude the paper
Retrieval of phase relation and emission profile of quantum cascade laser frequency combs
The major development recently undergone by quantum cascade lasers has
effectively extended frequency comb emission to longer-wavelength spectral
regions, i.e. the mid and far infrared. Unlike classical pulsed frequency
combs, their mode-locking mechanism relies on four-wave mixing nonlinear
processes, with a temporal intensity profile different from conventional
short-pulses trains. Measuring the absolute phase pattern of the modes in these
combs enables a thorough characterization of the onset of mode-locking in
absence of short-pulses emission, as well as of the coherence properties. Here,
by combining dual-comb multi-heterodyne detection with Fourier-transform
analysis, we show how to simultaneously acquire and monitor over a wide range
of timescales the phase pattern of a generic frequency comb. The technique is
applied to characterize a mid-infrared and a terahertz quantum cascade laser
frequency comb, conclusively proving the high degree of coherence and the
remarkable long-term stability of these sources. Moreover, the technique allows
also the reconstruction of electric field, intensity profile and instantaneous
frequency of the emission.Comment: 20 pages. Submitted to Nature Photonic
- …