Neuromorphic, Digital and Quantum Computation with Memory Circuit Elements

Memory effects are ubiquitous in nature and the class of memory circuit elements - which includes memristors, memcapacitors and meminductors - shows great potential to understand and simulate the associated fundamental physical processes. Here, we show that such elements can also be used in electronic schemes mimicking biologically-inspired computer architectures, performing digital logic and arithmetic operations, and can expand the capabilities of certain quantum computation schemes. In particular, we will discuss few examples where the concept of memory elements is relevant to the realization of associative memory in neuronal circuits, spike-timing-dependent plasticity of synapses, digital and field-programmable quantum computing

The computational power and complexity of discrete feedforward neural networks

The number of binary functions that can be defined on a set of L vectors in R^N equals 2^L . For L>N the total number of threshold functions in N-dimensional space grows polynomially (2^N(N-1))while the total number of Boolean functions, definable on N binary inputs, growsexponentially ( 2^2^2), and as N increases a percentage of threshold functions in relation to the total number of Boolean functions - goes to zero. This means that for the realization of a majority of tasks a neural network must possess at least two or three layers. The examples of small computational problems are arithmetic functions, like multiplication, division, addition, exponentiation or comparison and sorting. This article analyses some aspects of two- and more than two layers of threshold and Boolean circuits (feedforward neural nets), connected with their computational power and node, edge and weight complexity

Indicating Asynchronous Array Multipliers

Multiplication is an important arithmetic operation that is frequently encountered in microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of many indicating asynchronous array multipliers, which are inherently elastic and modular and are robust to timing, process and parametric variations. We consider the physical realization of many indicating asynchronous array multipliers using a 32/28nm CMOS technology. The weak-indication array multipliers comprise strong-indication or weak-indication full adders, and strong-indication 2-input AND functions to realize the partial products. The multipliers were synthesized in a semi-custom ASIC design style using standard library cells including a custom-designed 2-input C-element. 4x4 and 8x8 multiplication operations were considered for the physical implementations. The 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshake protocols were utilized for data communication, and the delay-insensitive dual-rail code was used for data encoding. Among several weak-indication array multipliers, a weak-indication array multiplier utilizing a biased weak-indication full adder and the strong-indication 2-input AND function is found to have reduced cycle time and power-cycle time product with respect to RTZ and RTO handshaking for 4x4 and 8x8 multiplications. Further, the 4-phase RTO handshaking is found to be preferable to the 4-phase RTZ handshaking for achieving enhanced optimizations of the design metrics.Comment: arXiv admin note: text overlap with arXiv:1903.0943

RTD based logic circuits using generalized threshold gates

Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from threshold gates (TGs). The MOBILE realization of generalized threshold gates is being investigated. Multi-Threshold Threshold Gates (MTTGs) have been proposed which further increase the functionality of the original TGs. Recently, we have proposed a novel MOBILE circuit topology obtained by fundamental properties of threshold functions. This paper describes the design of n-bit adders using these novel MOBILE circuit topologies. A comparison with designs based on TGs and MTTGs is carried out showing advantages in terms of speed and power delay product and device counts.España, Gobierno TEC2007-67245Junta de Andalucía EXC/2007/TIC-296

Realization of Analog Wavelet Filter using Hybrid Genetic Algorithm for On-line Epileptic Event Detection

© 2020 The Author(s). This open access work is licensed under a Creative Commons Attribution 4.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/.As the evolution of traditional electroencephalogram (EEG) monitoring unit for epilepsy diagnosis, wearable ambulatory EEG (WAEEG) system transmits EEG data wirelessly, and can be made miniaturized, discrete and social acceptable. To prolong the battery lifetime, analog wavelet filter is used for epileptic event detection in WAEEG system to achieve on-line data reduction. For mapping continuous wavelet transform to analog filter implementation with low-power consumption and high approximation accuracy, this paper proposes a novel approximation method to construct the wavelet base in analog domain, in which the approximation process in frequency domain is considered as an optimization problem by building a mathematical model with only one term in the numerator. The hybrid genetic algorithm consisting of genetic algorithm and quasi-Newton method is employed to find the globally optimum solution, taking required stability into account. Experiment results show that the proposed method can give a stable analog wavelet base with simple structure and higher approximation accuracy compared with existing method, leading to a better spike detection accuracy. The fourth-order Marr wavelet filter is designed as an example using Gm-C filter structure based on LC ladder simulation, whose power consumption is only 33.4 pW at 2.1Hz. Simulation results show that the design method can be used to facilitate low power and small volume implementation of on-line epileptic event detector.Peer reviewe