Charge Offset Stability in Si Single Electron Devices with Al Gates

We report on the charge offset drift (time stability) in Si single electron devices (SEDs) defined with aluminum (Al) gates. The size of the charge offset drift (0.15 $e$) is intermediate between that of Al/AlO$_x$/Al tunnel junctions (greater than 1 $e$) and Si SEDs defined with Si gates (0.01 $e$). This range of values suggests that defects in the AlO$_x$ are the main cause of the charge offset drift instability

A silicon-based single-electron interferometer coupled to a fermionic sea

We study Landau-Zener-Stueckelberg-Majorana (LZSM) interferometry under the influence of projective readout using a charge qubit tunnel-coupled to a fermionic sea. This allows us to characterise the coherent charge qubit dynamics in the strong-driving regime. The device is realised within a silicon complementary metal-oxide-semiconductor (CMOS) transistor. We first read out the charge state of the system in a continuous non-demolition manner by measuring the dispersive response of a high-frequency electrical resonator coupled to the quantum system via the gate. By performing multiple fast passages around the qubit avoided crossing, we observe a multi-passage LZSM interferometry pattern. At larger driving amplitudes, a projective measurement to an even-parity charge state is realised, showing a strong enhancement of the dispersive readout signal. At even larger driving amplitudes, two projective measurements are realised within the coherent evolution resulting in the disappearance of the interference pattern. Our results demonstrate a way to increase the state readout signal of coherent quantum systems and replicate single-electron analogues of optical interferometry within a CMOS transistor

Electric-field tuning of the valley splitting in silicon corner dots

We perform an excited state spectroscopy analysis of a silicon corner dot in a nanowire field-effect transistor to assess the electric field tunability of the valley splitting. First, we demonstrate a back-gate-controlled transition between a single quantum dot and a double quantum dot in parallel that allows tuning the device in to corner dot formation. We find a linear dependence of the valley splitting on back-gate voltage, from $880~\mu \text{eV}$ to $610~\mu \text{eV}$ with a slope of $-45\pm 3~\mu \text{eV/V}$ (or equivalently a slope of $-48\pm 3~\mu \text{eV/(MV/m)}$ with respect to the effective field). The experimental results are backed up by tight-binding simulations that include the effect of surface roughness, remote charges in the gate stack and discrete dopants in the channel. Our results demonstrate a way to electrically tune the valley splitting in silicon-on-insulator-based quantum dots, a requirement to achieve all-electrical manipulation of silicon spin qubits.Comment: 5 pages, 3 figures. In this version: Discussion of model expanded; Fig. 3 updated; Refs. added (15, 22, 32, 34, 35, 36, 37

Towards low-dimensional hole systems in Be-doped GaAs nanowires

GaAs was central to the development of quantum devices but is rarely used for nanowire-based quantum devices with InAs, InSb and SiGe instead taking the leading role. p-type GaAs nanowires offer a path to studying strongly-confined 0D and 1D hole systems with strong spin-orbit effects, motivating our development of nanowire transistors featuring Be-doped p-type GaAs nanowires, AuBe alloy contacts and patterned local gate electrodes towards making nanowire-based quantum hole devices. We report on nanowire transistors with traditional substrate back-gates and EBL-defined metal/oxide top-gates produced using GaAs nanowires with three different Be-doping densities and various AuBe contact processing recipes. We show that contact annealing only brings small improvements for the moderately-doped devices under conditions of lower anneal temperature and short anneal time. We only obtain good transistor performance for moderate doping, with conduction freezing out at low temperature for lowly-doped nanowires and inability to reach a clear off-state under gating for the highly-doped nanowires. Our best devices give on-state conductivity 95 nS, off-state conductivity 2 pS, on-off ratio ~$10^{4}$, and sub-threshold slope 50 mV/dec at T = 4 K. Lastly, we made a device featuring a moderately-doped nanowire with annealed contacts and multiple top-gates. Top-gate sweeps show a plateau in the sub-threshold region that is reproducible in separate cool-downs and indicative of possible conductance quantization highlighting the potential for future quantum device studies in this material system

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

We present a novel reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consist of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture

A hybrid metal/semiconductor electron pump for quantum metrology

Electron pumps capable of delivering a current higher than 100pA with sufficient accuracy are likely to become the direct mise en pratique of the possible new quantum definition of the ampere. Furthermore, they are essential for closing the quantum metrological triangle experiment which tests for possible corrections to the quantum relations linking e and h, the electron charge and the Planck constant, to voltage, resistance and current. We present here single-island hybrid metal/semiconductor transistor pumps which combine the simplicity and efficiency of Coulomb blockade in metals with the unsurpassed performances of silicon switches. Robust and simple pumping at 650MHz and 0.5K is demonstrated. The pumped current obtained over a voltage bias range of 1.4mV corresponds to a relative deviation of 5e-4 from the calculated value, well within the 1.5e-3 uncertainty of the measurement setup. Multi-charge pumping can be performed. The simple design fully integrated in an industrial CMOS process makes it an ideal candidate for national measurement institutes to realize and share a future quantum ampere