Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias

Este trabalho explora métodos para realizar o posicionamento de um tipo particular de circuitos VLSI conhecido como circuito 3D (três dimensões).. Diferente de trabalhos anteriores, este artigo aborda o problema de posicionamento 3D considerando as conexões verticais (chamadas 3D-Vias) e as limitações impostas pelas mesmas. Foi realizado um ?uxo completo de posicionamento, iniciando pelo tratamento de pinos de entrada e saída (E/S) e seguido com posicionamento global, posicionamento detalhado e posicionamento das 3D-Vias. A primeira etapa busca a distribuição os pinos de E/S de maneira equilibrada objetivando auxiliar o posicionamento para obter uma quantidade reduzida de 3D-Vias. O mecanismo de posicionamento global baseado no algorítmo de Quadratic Placement considera informações fornecidos pela tecnologia de fabricação e requisito de espaçamento de 3D-Vias para reduzir o comprimento das conexões e equilibrar a distribuição das células em 3D. Conexões críticas podem ser tratadas através da inserção de redes arti?ciais que auxiliam a evitar que 3D-Vias sejam usadas em sua implementação. Finalmente, as 3D-Vias são posicionadas por um algorítmo rápido baseado na legalização Tetris. O framework completo reforça os potenciais benefícios dos circuitos 3D para reduzir o comprimento das co- nexões e apresenta algorítmos e?cientes projetados para circuitos 3D que podem ser incorporados em novas ferramentas de CAD

A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits

Abstract. This paper presents an algorithm for I/O pins partitioning and placement targeting 3D circuits. The method starts from a standard 2D placement of the pins around a flat rectangle and outputs a 3D representation of the circuit composed of a set of tiers and pins placed at the four sides of the resulting cube. The proposed algorithm targets a balanced distribution of the I/Os that is required both for accommodating the pins evenly as well as to serve as an starting point for cell placement algorithms that are initially guided by I/O's locations, such as analytical placers. Moreover, the I/O partitioning tries to set pins in such a way the it allows the cell placer to reach a reduced number of 3D-Vias. The method works in two phases: first the I/O partitioning considering the logic distances as weights; second, fix the I/Os and perform partitioning of the cells. The experimental results show the effectiveness of the approach on balance and number of 3D-Vias compared to simplistic methods for I/O partitioning, including traditional min-cut algorithms. Since our method contains the information of the whole circuit compressed in a small graph, it could actually improve the partitioning algorithm at the expense of more CPU time. Additional experiments demonstrated that the method could be adapted to further reduce the number of 3D-Vias if the I/O pin balance constraint can be relaxed

Three-dimensional place and route for FPGAs

Abstract – We present timing-driven partitioning and simulated annealing based placement algorithms together with a detailed routing tool for 3D FPGA integration. The circuit is first divided into layers with limited number of inter-layer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. Experimental results show on average a total decrease of 21 % in wire-length and 24 % in delay, can be achieved over traditional 2D chips, when five layers are used in 3D integration. I

Three-dimensional place and route for FPGAs

Abstract—We present timing-driven partitioning and simulated annealing based placement algorithms together with a detailed routing tool for 3D FPGA integration. The circuit is first divided into layers with limited number of inter-layer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. Experimental results show on average a total decrease of 25 % in wire-length and 35% in delay, can be achieved over traditional 2D chips, when 10 layers are used in 3D integration. Index Terms—Field programmable gate arrays, threedimensional circuits, routing, timing-driven placement