Stochastic resonance exploration in current-driven ReRAM devices

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Advances in emerging resistive random-access memory (ReRAM) technology show promise for its use in future computing systems, enabling neuromorphic and memory-centric computing architectures. However, one aspect that holds back the widespread practical use of ReRAM is the behavioral variability of resistive switching devices. In this context, a radically new path towards ReRAM-based electronics concerns the exploitation of noise and the Stochastic Resonance (SR) phenomenon as a mechanism to mitigate the impact of variability. While SR has been already demonstrated in ReRAM devices and its potential impact has been analyzed for memory applications, related works have only focused on voltage input signals. In this work we present preliminary results concerning the exploration of SR in current-driven ReRAM devices, commercially available by Knowm Inc. Our results indicate that additive noise of amplitude s = 0.125uA can stabilize the cycling performance of the devices, whereas higher noise amplitude improves the HRS-LRS resistance window, thus could affect positively the Bit Error Rate (BER) metric in ReRAM memory applications.Supported by the Chilean research grants FONDECYT INICIACION 11180706 and ANID-Basal FB0008, and by the Spanish MCIN grants PID2019-105658RB-I00, and MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33.Peer ReviewedPostprint (author's final draft

On the variability-aware design of memristor-based logic circuits

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Ever since the advent of the first TiO 2 -based memristor and the respective linear model published by Hewlett-Packard Labs, several behavioral models of memristors have been published. Such models capture the fundamental characteristics of resistive switching behavior through simple equations and rules, so they received a lot of attention and contributed significantly to the fast progress of research in this new and emerging device technology field. However, while this technology is maturing, accurate physics-based models are being developed, which go deeper into the device dynamics and capture more details than what just would be the fundamentals: i.e. parasitics of the device structure, variability of threshold voltages and resistance states, temperature dependency, dynamic current fluctuations, etc. In this work we build upon such a physics-based model of a bipolar metal-oxide resistive RAM device, showing how to take into account device variability and its significance in evaluation of processing circuits. With the Cadence Virtuoso suite, we focus on a family of memristive logic gate implementations showing that read & write errors can emerge due to both variability and state-drift impact, features rarely seen so far in results shown in other relevant published works.Peer ReviewedPostprint (author's final draft

Variability-tolerant memristor-based ratioed logic in crossbar array

The final publication is available at ACM via http://dx.doi.org/10.1145/3232195.3232213The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this de- vice technology, with several emerging applications including that of logic circuits. Several memristive logic families have been pro- posed, each with different attributes, in the current quest for energy- efficient computing systems of the future. However, limited en- durance of memristor devices and variations (both cycle-to-cycle and device-to-device) are important parameters to be considered in the evaluation of such logic families. In this work we build upon an accurate physics-based model of a bipolar metal-oxide resistive RAM device (supporting parasitics of the device structure and va- riability of switching voltages and resistance states) and use it to show how performance of memristor-based logic circuits can de degraded owing to both variability and state-drift impact. Based on previous work on CMOS-like memristive logic circuits, we propose a memristive ratioed logic scheme, which is crossbar-compatible, i.e. suitable for in-/near-memory computing, and tolerant to device variability, while also it does not affect the device endurance since computations do not involve switching the memristor states. As a figure of merit, we compare such new logic scheme with MAGIC, focusing on the universal NOR logic gate.Peer ReviewedPostprint (author's final draft

Mathematical simulation of memristive for classification in machine learning

Over the last few years, neuromorphic computation has been a widely researched topic. One of the neuromorphic computation elements is the memristor. The memristor is a high density, analogue memory storage, and compliance with Ohm's law for minor potential changes. Memristive behaviour imitates synaptic behaviour. It is a nanotechnology that can reduce power consumption, improve synaptic modeling, and reduce data transmission processes. The purpose of this paper is to investigate a customized mathematical model for machine learning algorithms. This model uses a computing paradigm that differs from standard Von-Neumann architectures, and it has the potential to reduce power consumption and increasing performance while doing specialized jobs when compared to regular computers. Classification is one of the most interesting fields in machine learning to classify features patterns by using a specific algorithm. In this study, a classifier based memristive is used with an adaptive spike encoder for input data. We run this algorithm based on Anti-Hebbian and Hebbian learning rules. These investigations employed two of datasets, including breast cancer Wisconsin and Gaussian mixture model datasets. The results indicate that the performance of our algorithm that has been used based on memristive is reasonably close to the optimal solution

Exploring the “resistance change per energy unit” as universal performance parameter for resistive switching devices

© Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/Resistive switching (RS) device (memristor) technology is continuously maturing towards industrial establishment. There are RS devices that demonstrate an “incremental” (analog) switching behavior, whereas others change their state in a binary form. The final achieved resistance is generally a function of the applied pulse characteristics, i.e. amplitude and duration. However, variability —both from device to device but also from cycle to cycle— and the stochastic nature of internal RS phenomena, still hold back any universal tuning approach based solely on these two magnitudes, making also difficult the qualitative comparison between devices with different material compounds owing to the required SET/RESET voltages being dependent on the biasing conditions. In this work we demonstrate experimentally using commercial RS devices from Knowm Inc. that the switching energy is very insensitive to the biasing conditions. We explored experimentally the SET-RESET behavior of bipolar RS devices from the energy point of view. We figured out the quantitative effect of the injected energy to the resistive state of the devices, and proposed an analytical model to explain our observations in the energy consumed by the device during the switching process. Our results lay the foundations for the definition of “resistance change per energy unit” as a performance parameter for this emerging device technology.Peer ReviewedPostprint (author's final draft

Shortest path computing in directed graphs with weighted edges mapped on random networks of memristors

Electronic version of an article published as [Fernandez, Carlos, Ioannis Vourkas, and Antonio Rubio. "Shortest Path Computing in Directed Graphs with Weighted Edges Mapped on Random Networks of Memristors." Parallel Processing Letters 30.01 (2020): 2050002] [https://doi.org/10.1142/S0129626420500024] © [copyright World Scientific Publishing Company] [https://www.worldscientific.com/worldscinet/ppl]To accelerate the execution of advanced computing tasks, in-memory computing with resistive memory provides a promising solution. In this context, networks of memristors could be used as parallel computing medium for the solution of complex optimization problems. Lately, the solution of the shortest-path problem (SPP) in a two-dimensional memristive grid has been given wide consideration. Some still open problems in such computing approach concern the time required for the grid to reach to a steady state, and the time required to read the result, stored in the state of a subset of memristors that represent the solution. This paper presents a circuit simulation-based performance assessment of memristor networks as SPP solvers. A previous methodology was extended to support weighted directed graphs. We tried memristor device models with fundamentally different switching behavior to check their suitability for such applications and the impact on the timely detection of the solution. Furthermore, the requirement of binary vs. analog operation of memristors was evaluated. Finally, the memristor network-based computing approach was compared to known algorithmic solutions to the SPP over a large set of random graphs of different sizes and topologies. Our results contribute to the proper development of bio-inspired memristor network-based SPP solvers.This work was supported by the Chilean research grants CONICYT REDES ETAPA INICIAL Convocatoria 2017 No. REDI170604, CONICYT BASAL FB0008, and by the Spanish MINECO and ERDF (TEC2016-75151-C3-2-R).Peer ReviewedPostprint (author's final draft

Memristors for the Curious Outsiders

We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2-terminal passive component with a dynamic resistance depending on an internal parameter. We provide an brief historical introduction, as well as an overview over the physical mechanism that lead to memristive behavior. This review is meant to guide nonpractitioners in the field of memristive circuits and their connection to machine learning and neural computation.Comment: Perpective paper for MDPI Technologies; 43 page