Optimal microscale water cooled heat sinks for targeted alleviation of hotspot in microprocessors

This paper was presented at the 4th Micro and Nano Flows Conference (MNF2014), which was held at University College, London, UK. The conference was organised by Brunel University and supported by the Italian Union of Thermofluiddynamics, IPEM, the Process Intensification Network, the Institution of Mechanical Engineers, the Heat Transfer Society, HEXAG - the Heat Exchange Action Group, and the Energy Institute, ASME Press, LCN London Centre for Nanotechnology, UCL University College London, UCL Engineering, the International NanoScience Community, www.nanopaprika.eu.Hotspots in microprocessors arise due to non-uniform utilization of the underlying integrated circuits during chip operation. Conventional liquid cooling using microchannels leads to undercooling of the hotspot areas and overcooling of the background area of the chip resulting in excessive temperature gradients across the chip. These in turn adversely affect the chip performance and reliability. This problem becomes even more acute in multi-core processors where most of the processing power is concentrated in specific regions of the chip called as cores. We present a 1-dimensional model for quick design of a microchannel heat sink for targeted, single-phase liquid cooling of hotspots in microprocessors. The method utilizes simplifying assumptions and analytical equations to arrive at the first estimate of a microchannel heat sink design that distributes the cooling capacity of the heat sink by adapting the coolant flow and microchannel size distributions to the microprocessor power map. This distributed cooling in turn minimizes the chip temperature gradient. The method is formulated to generate a heat sink design for an arbitrary chip power map and hence can be readily utilized for different chip architectures. It involves optimization of microchannel widths for various zones of the chip power map under the operational constraints of maximum pressure drop limit for the heat sink. Additionally, it ensures that the coolant flows uninterrupted through its entire travel length consisting of microchannels of varying widths. The resulting first design estimate significantly reduces the computational effort involved in any subsequent CFD analysis required to fine tune the design for more complex flow situations arising, for example, in manifold microchannel heat sinks

Towards on-chip time-resolved thermal mapping with micro-/nanosensor arrays

In recent years, thin-film thermocouple (TFTC) array emerged as a versatile candidate in micro-/nanoscale local temperature sensing for its high resolution, passive working mode, and easy fabrication. However, some key issues need to be taken into consideration before real instrumentation and industrial applications of TFTC array. In this work, we will demonstrate that TFTC array can be highly scalable from micrometers to nanometers and that there are potential applications of TFTC array in integrated circuits, including time-resolvable two-dimensional thermal mapping and tracing the heat source of a device. Some potential problems and relevant solutions from a view of industrial applications will be discussed in terms of material selection, multiplexer reading, pattern designing, and cold-junction compensation. We show that the TFTC array is a powerful tool for research fields such as chip thermal management, lab-on-a-chip, and other novel electrical, optical, or thermal devices

A new tightly-coupled transient electro-thermal simulation method for power electronics

Paper no. 224This paper presents a new transient electro-thermal (ET) simulation method for fast 3D chip-level analysis of power electronics with field solver accuracy. The metallization stacks are meshed and solved with 3D field solver using nonlinear temperature-dependent parameters, and the active devices are modeled with nonlinear tabular compact models to avoid time-consuming TCAD simulation. The main contributions include: 1) A tightly-coupled formulation that solves the electrical and thermal responses simultaneously for better convergence property; 2) Explicit account of capacitive effects, including interconnect parasitic capacitance and gate capacitance of power devices, to improve modeling accuracy in highfrequency applications; 3) A specialized transient solver based on the matrix exponential method (MEXP) to address the multi-scale problem caused by the considerably different time scales in electrical and thermal dynamics. Numerical experiments have demonstrated the advantages of the proposed co-simulation framework.postprin

A survey of emerging architectural techniques for improving cache energy consumption

The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students

Fundamental Characterization of Low Dimensional Carbon Nanomaterials for 3D Electronics Packaging

Transistor miniaturization has over the last half century paved the way for higher value electronics every year along an exponential pace known as \u27Moore\u27s law\u27. Now, as the industry is reaching transistor features that no longer makes economic sense, this way of developing integrated circuits (ICs) is coming to its definitive end. As a solution to this problem, the industry is moving toward higher hanging fruits that can enable larger sets of functionalities and ensuring a sustained performance increase to continue delivering more cost-effective ICs every product cycle. These design strategies beyond Moore\u27s law put emphasis on 3D stacking and heterogeneous integration, which if implemented correctly, will deliver a continued development of ICs for a foreseeable future. However, this way of building semiconductor systems does bring new issues to the table as this generation of devices will place additional demands on materials to be successful. The international roadmap of devices and systems (IRDS) highlights the need for improved materials to remove bottlenecks in contemporary as well as future systems in terms of thermal dissipation and interconnect performance. For this very purpose, low dimensional carbon nanomaterials such as graphene and carbon nanotubes (CNTs) are suggested as potential candidates due to their superior thermal, electrical and mechanical properties. Therefore, a successful implementation of these materials will ensure a continued performance to cost development of IC devices.This thesis presents a research study on some fundamental materials growth and reliability aspects of low dimensional carbon based thermal interface materials (TIMs) and interconnects for electronics packaging applications. Novel TIMs and interconnects based on CNT arrays and graphene are fabricated and investigated for their thermal resistance contributions as well electrical performance. The materials are studied and optimized with the support of chemical and structural characterization. Furthermore, a reliability study was performed which found delamination issues in CNT array TIMs due to high strains from thermal expansion mismatches. This study concludes that CNT length is an important factor when designing CNT based systems and the results show that by further interface engineering, reliability can be substantially improved with maintained thermal dissipation and electrical performance. Additionally, a heat treatment study was made that enables improvement of the bulk crystallinity of the materials which will enable even better performance in future applications

Fabrication and Characterisation of Carbon Nanotube Array Thermal Interface Materials

The performance of electronic devices has long been limited by thermal dissipation which will result in device failure if not handled properly. The next generation of integrated circuit (IC) devices will feature new packaging technologies like heterogeneous integration as well as 3D stacking which entails additional emphasis on the thermal management solutions employed. Therefore, new materials are in demand to meet the increased thermal dissipation requirements to allow continued scaling in terms of cost per performance and increased device reliability.The largest bottleneck in thermal dissipation originates from thermal interfaces between different surfaces. For this purpose thermal interface materials (TIMs) are used to conform and bridge the interface and thereby alleviate the thermal dissipation restrictions in the interface. However, commercially available TIMs are either of metallic or polymeric nature which implies a compromise between thermal performance and reliability. Carbon nanotube (CNT) arrays have been suggested as a future potential material in order to achieve a TIM with superior thermal and mechanical properties that would ensure simultaneous high thermal performance and reliability. However, proper bonding solutions are still to be developed in order to apply CNT array TIMs in thermal dissipation applications and to ensure a successful market realisation.\ua0This thesis first outlines the field by presenting a thorough literature review of organic functionalization methods for CNT array TIMs. Three different approaches are identified: polymer embedding, polymer bonding and self-assembly based functionalization. The thesis then presents two experimental studies on CNT array TIMs. The first focuses on the development and characterisation of a CNT array TIM using a novel self-assembly based bonding method by employing epoxy chemistry for covalent anchoring. The second part focuses on a reliability study of a CNT array TIM assembled using a polymer bonding method, which is an aspect that previously has been overlooked. The results from the reliability study gave indications that themechanical bonding between the CNT array and the growth substrate was susceptible for rapid degradation and further research is required in this field to address this challenge

Design and test of shape memory alloy fins for self-adaptive liquid cooling device

Thermal management complexity increases in high-performance chips, where the heat loads vary spatially and temporally, while liquid cooling systems are usually designed for most stringent stationary conditions. Several works developed heat transfer enhancement techniques to increase the cooling capacity of liquid cooled heat sinks, but pumping power is increased in a permanent way due to the addition of elements within the channels. Here, a liquid cooling self-adaptive heat sink that can efficiently adapt the distribution of its heat extraction capacity to time dependent and non-uniform heat load scenarios is proposed. Numerical design of the mesoscale cooling device with bimorph metal/SMA fins, definition of the fabrication and training procedure of the SMA fins to reach the desired behavior and experimental assessment is presented. The capacity of the self-adaptive fins to locally boost the heat transfer is numerically and experimentally demonstrated. Results obtained show that the self-adaptive fins can improve the temperature uniformity by 63% with respect to plain channel. The reduction in thermal resistance using bimorph metal/SMA fins sample allows the surface maximum temperature gradient to remain almost constant although heat flux increases. Energy savings are maximized in applications where partial load intervals contributes significantly to the overall operating period.The research leading to these results has been performed within the project Indústria del Coneixement 2018, PROD-00071 “Experimental demonstration and commercial viability of an energy efficient universal cooling scheme”. It has been co-financed by the European Union through the European Regional Development Fund (FEDER) and has the support of the Secretaria d’Universitats i Recerca from Departament d’Empresa i Coneixement of the Generalitat de Catalunya

Thermal-mechanical analysis of a power module with parametric model order reduction

This paper presents parametric model order reduction (pMOR) by the Lagrange approach of matrix interpolation for the thermal-mechanical and reliability study of a power electronics module (PEM) with nonlinear behaviours. Most pre-vious research in model order reduction (MOR) studies reports thermal-mechanical simulations using a sequentially coupled method. In this research, a direct-coupled thermal-mechanical analysis, which simultaneously solves the thermal and structural governing equations, has been used to obtain thermal and defor-mation results. Furthermore, for pMOR, the linear approach of matrix interpolation is limited to linear changes between sampled-parametric points. Hence, a new way of interpolating system matrices using the Lagrange interpolation method has been adopted to implement the matrix interpolation efficiently. The parametric reduced-order model (pROM) solution by the Lagrange approach of matrix interpolation agrees well with the full-order model (FOM) and takes similar computational time as the linear (bi-linear) approach of matrix interpolation. pROM simulations offer up to 85.5 % reduction in computational time