Study on Preparation and Reflow Process of Nano Glass Powder for MEMS Encapsulations

封装一直是MEMS器件的重难点，封装的好坏直接决定器件的成败。受成本、方便性、封装性能、工艺复杂程度、器件大小等诸多因素的影响，使用盖帽的圆片级封装成为一种明智、新颖和备受欢迎的方法，是MEMS器件封装的趋势。玻璃盖帽具有寄生电容小、和硅键合容易、绝热性能好等优点，是常用的封装盖帽。特别是高频RF传感器，玻璃盖帽因其良好的电学隔离作用，成为盖帽的最佳选择。然而玻璃盖帽的制作却非常困难。传统玻璃回流工艺是如今较好的一种玻璃盖帽制作方式，但仍然有很多不足，如抛光容易碎片、回流时间长、有最小线宽的限制、需要高真空阳极键合等。 本文以玻璃盖帽为出发点，研究了玻璃粉回流工艺的若干问题。为了获得纳米玻璃...Packaging which directly determines the success or failure of the device has always been the major difficulty in MEMS devices. Effected by many factors such as cost, convenience, package performance, process complexity, device size, wafer level packaging using a cap becomes a wise, novel and popular way, and it is the inevitable trend of MEMS package. Due to the advantages of small parasitic capac...学位：工学硕士院系专业：航空航天学院_机械制造及其自动化学号：1992014115287

The development and evaluation of RF TSV for 3D IPD applications

In this paper, Silex Microsystems, the world's largest Pure-Play MEMS foundry, together with partners TNO and VTT, present our recent advancements in RF through silicon Vias (TSV) for 3D integrated passive devices (IPD) applications, achieved in conjunction with the European consortium EPAMO. A novel open TSV fabrication process on 200 mm diameter 305 μm thick High Resistivity wafers has been used to demonstrated High Aspect Ratio Through Silicon Vias (HAR TSV), focusing on tight pitch, resulting in 36 TSV/mm2 Via density. 305 μm wafer thickness enables the fabrication of rigid interposers, an advancement in the commercialization of 3D packaging technology. The fabrication includes double sided deep reactive ion etching (DRIE), developments and evaluation on various conformal high aspect ratio (HAR) plating seedlayer processes, and void-free TSV Cu plating of open rigid TSV structures and bonding to glass wafers for characterization. The electrical characterization of the fabricated devices was performed by VTT with excellent measured RF properties: in specific, low RF losses as well as low DC resistances of less than 20 mOhm/TSV. Several different coplanar waveguide (CPW) test vehicles and other RF TSV test structures together with Daisy Chain and parasitic Capacitance test structures were designed, fabricated and evaluated. The loss of a single coplanar TSV transition is less than 0.04 dB @ 5 GHz, which is considered to be very small. The developed TSV technology was also employed to fabricate 3D toroidal inductors. These inductors were characterized by TNO showing high Q-factor (>30) and self-resonance frequency (> 6 GHz) for 3D inductors in the range of 1-15 nH. 1 and 2 port inductor temperature characteristics over temperature interval from room temperature to 111°C are reported. A fabrication integration scheme for fully integrated RF-IPD with 3D TSV based inductors and high ohmic polysilicon (p-Si) resistors and piezoelectric (PZT) metal-insulator-metal (MIM) capacitors are discussed. Outlook for improvements using integrated high frequency magnetic flux materials and commercialization aspects are described. © 2013 IEEE