6,481 research outputs found

    AN EFFICIENT ERROR DETECTION AND CORRECTION METHOD FOR TIMING ERRORS

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    Timing errors are an important concern in nanometer CMOS technologies. A promising way to overcome the timing errors is the development of error detection and correction techniques. A local error detection and correction technique is done in this work. It is based on a new bit flipping flip flop. Whenever a timing error is detected, it is corrected by complementing the output of the corresponding flip flop. No extra circuitry is inserted in the design. Timing errors are identified and corrected within a single cycle and hence design complexity is reduced which results in reduced power consumption and low silicon area when compared to the earlier designs

    Theoretical and Experimental Analysis of a Randomized Algorithm for Sparse Fourier Transform Analysis

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    We analyze a sublinear RAlSFA (Randomized Algorithm for Sparse Fourier Analysis) that finds a near-optimal B-term Sparse Representation R for a given discrete signal S of length N, in time and space poly(B,log(N)), following the approach given in \cite{GGIMS}. Its time cost poly(log(N)) should be compared with the superlinear O(N log N) time requirement of the Fast Fourier Transform (FFT). A straightforward implementation of the RAlSFA, as presented in the theoretical paper \cite{GGIMS}, turns out to be very slow in practice. Our main result is a greatly improved and practical RAlSFA. We introduce several new ideas and techniques that speed up the algorithm. Both rigorous and heuristic arguments for parameter choices are presented. Our RAlSFA constructs, with probability at least 1-delta, a near-optimal B-term representation R in time poly(B)log(N)log(1/delta)/ epsilon^{2} log(M) such that ||S-R||^{2}<=(1+epsilon)||S-R_{opt}||^{2}. Furthermore, this RAlSFA implementation already beats the FFTW for not unreasonably large N. We extend the algorithm to higher dimensional cases both theoretically and numerically. The crossover point lies at N=70000 in one dimension, and at N=900 for data on a N*N grid in two dimensions for small B signals where there is noise.Comment: 21 pages, 8 figures, submitted to Journal of Computational Physic

    Study, definition and analysis of pilot/system performance measurements for planetary entry experiments

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    Definition analysis for experimental prediction of pilot performance during planetary entr

    Timing error tolerance in nanometer ICs

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    Abstract—Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency
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