2 research outputs found
A Family of Fault-Tolerant Efficient Indirect Topologies
© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.On the one hand, performance and fault-tolerance of interconnection networks are key design issues for high performance computing (HPC) systems. On the other hand, cost should be also considered. Indirect topologies are often chosen in the design of HPC systems. Among them, the most commonly used topology is the fat-tree. In this work, we focus on getting the maximum benefits from the network resources by designing a simple indirect topology with very good performance and fault-tolerance properties, while keeping the hardware cost as low as possible. To do that, we propose some extensions to the fat-tree topology to take full advantage of the hardware resources consumed by the topology. In particular, we propose three new topologies with different properties in terms of cost, performance and fault-tolerance. All of them are able to achieve a similar or better performance results than the fat-tree, providing also a good level of fault-tolerance and, contrary to most of the available topologies, these proposals are able to tolerate also faults in the links that connect to end nodes.This work was supported by the Spanish Ministerio de Economia y Competitividad (MINECO) and by FEDER funds under Grant TIN2012-38341-C04-01.Bermúdez Garzón, DF.; Gómez Requena, C.; Gómez Requena, ME.; López Rodríguez, PJ.; Duato Marín, JF. (2016). A Family of Fault-Tolerant Efficient Indirect Topologies. IEEE Transactions on Parallel and Distributed Systems. 27(4):927-940. https://doi.org/10.1109/TPDS.2015.2430863S92794027
Mesh-of-Trees Interconnection Network for an Explicitly Multi-Threaded Parallel Computer Architecture
As the multiple-decade long increase in clock rates starts to
slow down, main-stream general-purpose processors evolve towards
single-chip parallel processing.
On-chip interconnection networks are essential components of such
machines, supporting the communication between processors and
the memory system.
This task is especially challenging for some easy-to-program
parallel computers, which are designed with performance-demanding
memory systems.
This study proposes an interconnection network, with
a novel implementation of the Mesh-of-Trees (MoT) topology.
The MoT network is evaluated relative to metrics such as wire area
complexity, total register
count, bandwidth, network diameter, single switch delay, maximum
throughput per area, trade-offs between
throughput and latency, and post-layout performance.
It is also compared with some other traditional
network topologies, such as mesh, ring, hypercube, butterfly, fat
trees, butterfly fat trees, and replicated butterfly
networks.
Concrete results show that MoT provides
higher throughput and lower latency especially when the input
traffic (or the on-chip parallelism) is high, at comparable
area cost.
The layout of MoT network is evaluated using standard cell design
methodology. A prototype chip with 8-terminal MoT network
was taped out at technology and tested.
In the context of an easy-to-program single-chip parallel processor,
MoT network is
embedded in the eXplicit Multi-Threading (XMT) architecture, and
evaluated by running parallel applications.
In addition to the basic MoT architecture,
a novel hybrid extension of MoT is proposed, which allows
significant area savings with a small reduction in throughput