Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

EXPERIENCING THE EFFECTS OF CLOCK TRANSITION TIMES ON CLOCKED STORAGE ELEMENTS

Designing synchronous sequential circuits consisting of clocked storage elements such as flip-flops needs to observe stringent setup time and hold time constraints. If there is a timing violation, meaning the input data changes within the setup time and hold time window of the active clock edge, the results of the clocked storage elements could be unpredictable, a situation called metastable state. The cause and symptoms of metastable state are well established in the digital design literature. However, the effects of clock transition times such as rise time and fall time on the behavior of a synchronous sequential circuit are rarely discussed. This paper presents an experiment to demonstrate that the transition time of a clock signal can also affect the results of a clocked storage element. Understanding this effect is crucial for designing more robust complex high-speed digital systems consisting of clocked storage elements